Patent application number | Description | Published |
20080247235 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - Provided are a flash memory device and a method of driving the same for reading set information and stably storing the read set information in a latch. The method of driving the flash memory device includes applying power to the flash memory device, which includes a memory cell array for storing set information used to set an operating environment of the flash memory device. An initial read operation of the memory cell array is performed to read the set information. The set information read in the initial read operation is stored in a latch. It is determined whether the set information is normally stored in the latch based on set data input to the latch and set data output from the latch. | 10-09-2008 |
20080247247 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding operation environment settings, where the set information includes at least one bit. The method further includes performing an initial read operation on the memory cell array and judging a status of data, corresponding to the set information, read during the initial read operation to determine whether the initial read operation has passed or failed. Each bit of the set information is extended to n bits (where n is an integer equal to or greater than 2). The n bits are respectively stored in different input/output regions in the memory cell array. | 10-09-2008 |
20080253191 | FLASH MEMORY DEVICE AND SET-UP DATA INITIALIZATION METHOD - A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal. | 10-16-2008 |
20080298128 | METHOD OF STORING E-FUSE DATA IN FLASH MEMORY DEVICE - Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit. | 12-04-2008 |
20080298134 | METHOD OF READING CONFIGURATION DATA IN FLASH MEMORY DEVICE - Provided is a method of reading configuration data in a flash memory device, including a memory cell array which stores configuration data about an operating environment of the flash memory device. The method includes setting a read time of the configuration data to differ from a read time of normal data, and reading the configuration data. | 12-04-2008 |
20090027939 | MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT - Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips. | 01-29-2009 |
20090168526 | FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells. | 07-02-2009 |
20100002507 | FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed. | 01-07-2010 |
20100002508 | FLASH MEMORY DEVICE CONTROLLING COMMON SOURCE LINE VOLTAGE, PROGRAM-VERIFY METHOD, AND MEMORY SYSTEM - Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data. | 01-07-2010 |
20100220535 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced. | 09-02-2010 |
20100259993 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 10-14-2010 |
20110211393 | FLASH MEMORY DEVICE AND SET-UP DATA INITIALIZATION METHOD - A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal. | 09-01-2011 |
20110286278 | METHOD OF STORING E-FUSE DATA IN FLASH MEMORY DEVICE - Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit. | 11-24-2011 |
20120120731 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 05-17-2012 |
20120155184 | FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells. | 06-21-2012 |
20120320675 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 12-20-2012 |