Patent application number | Description | Published |
20100052952 | KEY SCANNING CIRCUIT - In a key scanning circuit, a key input unit has a parallel connection of a plurality of circuits having a series connection of resistors and switches between a power supply input terminal and a key scanning terminal. The resistors connected in parallel have different resistances. A current mirror has a first terminal connected to the key scanning terminal. A reference current source is connected between a second terminal of the current mirror and the power supply input terminal. | 03-04-2010 |
20100117740 | BROADBAND VOLTAGE CONTROLLED OSCILLATOR AND METHOD FOR GENERATING BROADBAND OSCILLATION FREQUENCY - The present invention relates to a broadband voltage controlled oscillator and a method for generating a broadband oscillation frequency; and, more particularly, to a broadband voltage controlled oscillator and a method for generating a broadband oscillation frequency capable of operating over a wide frequency band by including a weighted current cell to select two frequency band modes, generating various levels of total 64 oscillation frequencies by including a variable frequency tank and a capacitor bank, and further facilitating adjustment of the total 64 oscillation frequencies distributed over the wide frequency band by including a control signal generator for generating control signals each of which is applied to the weighted current cell, the variable frequency tank and the capacitor bank by a BDD(Binary Decision Diagram) technique. | 05-13-2010 |
20100150041 | WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION - Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit. | 06-17-2010 |
20110140943 | Digital-analog converter - In order to reduce a current mismatch by laying-out the bias circuit of current cells adjacent to each other in a common current centroid manner or connecting the output lines of the current cells in a tournament manner, there is provided a digital-analog converter in which a plurality of current cells are two dimensionally and symmetrically disposed according to a previously determined order, the digital-analog converter including: a first current cell group including a portion of the plurality of current cells; and a second current cell group including the rest of the plurality of current cells, not included in the first current cell group, the outputs of each current cell of the first current cell group being connected to the outputs of each current cell of the second current cell group in a tournament manner, wherein each of the plurality of current cells includes: a switch circuit switching the output and block of a unit current according to an input signal; and a bias circuit mirroring current supplied according to the switching of the switch circuit and converting the current into the unit current, the bias circuit of two current cells adjacent to each other among the plurality of current cells being laid-out in a common current centroid manner. | 06-16-2011 |
20110193415 | WIRELESS ENERGY TRANSMISSION STRUCTURE - Disclosed is a wireless energy transmission structure which includes a disc part including a first conductor plate and a second conductor plate which are spaced to face each other and a dielectric material inserted between the first conductor plate and the second conductor plate, and generating an electric field between the first conductor plate and the second conductor plate; and a ring-shaped wire part one end of which is connected to the first conductor plate and the other end of which is connected to the second conductor plate, and having a meta structure in which a plurality of meta cells is repetitively arranged so as to induce a magnetic field using the electric field, so that the wireless energy transmission structure is reduced in size and is improved in transmission distance and transmission efficiency. | 08-11-2011 |
20110241609 | WIRELESS ENERGY TRANSMISSION STRUCTURE - Disclosed herein is a wireless energy transmission structure, which includes a printed circuit board, a disk section, and a wire section. The printed circuit board is formed in a ring type, the disk section is constituted by a first conductive plate and a second conductive plate formed on portions of the printed circuit board corresponding to each other to be spaced by a predetermined gap and a dielectric material inserted between the first conductive plate and the second conductive plate, and the wire section is constituted by a plurality of meta cells having a meta material structure, which are repetitively formed to surround the exterior and interior of the printed circuit board and a transmission line connected to each of the first conductive plate and the second conductive plate and surround the plurality of meta cells. | 10-06-2011 |
20110266879 | APPARATUS FOR TRANSMITTING AND RECEIVING WIRELESS ENERGY USING META-MATERIAL STRUCTURES HAVING ZERO REFRACTIVE INDEX - Disclosed herein is an apparatus for transmitting and receiving wireless energy using meta-material structures having a zero refractive index. The apparatus includes a wireless energy transmission unit and a wireless energy reception unit. When external power is applied thereto, the wireless energy transmission unit generates wireless energy to be wirelessly transmitted, and then wirelessly transmits wireless energy, which is normally propagated radially when the generated wireless energy is transmitted, using a magnetic resonance method while concentrating the wireless energy in one direction. | 11-03-2011 |
20110267247 | APPARATUS FOR TRANSMITTING AND RECEIVING WIRELESS ENERGY USING META-MATERIAL STRUCTURES HAVING NEGATIVE REFRACTIVE INDEX - Disclosed herein is there is provided an apparatus for transmitting and receiving wireless energy using meta-material structures having a negative refractive index. The apparatus includes a wireless energy transmission unit and a wireless energy reception unit. The wireless energy transmission unit generates wireless energy to be wirelessly transmitted, and then wirelessly transmits wireless energy, which is normally propagated radially, using a magnetic resonance method while concentrating the wireless energy at a single point. The wireless energy reception unit wirelessly receives the wireless energy using the magnetic resonance method while concentrating the wireless energy at a single point. | 11-03-2011 |
20110298296 | RECTIFIER CIRCUIT OF WIRELESS POWER TRANSMISSION SYSTEM - Disclosed herein is a rectifier circuit of a wireless power transmission system, the rectifier circuit including: a rectifying unit rectifying an RF signal inputted through an RF input stage in a half-wave rectification type; an impedance matching unit installed between the RF input stage and the rectifying unit to match an impedance between the RF input stage and the rectifying unit; and a filtering unit filtering the signal rectified by the rectifying unit, thereby removing a radio frequency component and reducing a radio frequency ringing phenomenon, and thus, improving the efficiency of the rectifier circuit. | 12-08-2011 |
20120038220 | WIRELESS POWER TRANSMISSION APPARATUS AND TRANSMISSION METHOD THEREOF - Disclosed herein are a wireless power transmission apparatus and a transmission method thereof. The wireless power transmission apparatus is configured to include a wireless power transmitter generating a wireless power signal to be wireless transmitted, wirelessly transmitting the generated wireless power signal by a magnetic resonance manner, receiving a reflection wireless power signal to determine whether or not a load apparatus is presented, and supplying power to the load apparatus; and a wireless power receiver connected to the load apparatus and receiving the transmitted wireless power signal by the magnetic resonance manner and supplying it to the connected load apparatus and reflecting the remaining wireless power signal to the wireless power transmitter, whereby a transmission apparatus can recognize a receiving environment and resonance characteristics are improved, without a separate communication device or a system. | 02-16-2012 |
20120146425 | WIRELESS POWER TRANSMISSION/RECEPTION APPARATUS AND METHOD - Disclosed herein is a wireless power transmission/reception apparatus. The wireless power transmission/reception apparatus includes a wireless power transmission unit configured to generate a wireless power signal to be transmitted, transmit the wireless power signal using magnetic resonance, receive a reflected wireless power signal from a wireless power reception unit, determine whether a load device is present, and transmit a wireless power signal if it is determined that the load device is present in such a way that impedance and output power depending on variation in a distance to the load device are automatically tracked, and wireless power is supplied to the load device in an optimized state. A wireless to power reception unit is connected to the load device, and configured to receive the wireless power signal, provide the wireless power signal to the load device, and reflect a reflected wireless power signal towards the wireless power transmission unit. | 06-14-2012 |
20120217926 | WIRELESS POWER TRANSFER - Disclosed herein is a wireless power transfer system. The wireless power transfer system includes a wireless power transmitter receiving power input from the outside to generate a wireless power signal to be transmitted in wireless and transmitting the generated wireless power signal in wireless by a magnetic resonance manner using an LC serial-parallel resonance circuit; a wireless power receiver installed in a charging device to receive the wireless power signal transmitted from the wireless power transmitter by the magnetic resonance manner using the LC serial-parallel resonance circuit and output the received wireless power signal; and a charging circuit installed in the charging device to allow the power output from the wireless power receiver to charge an embedded battery, thereby making it possible to efficiently provide power in wireless. | 08-30-2012 |
20120242158 | WIRELESS POWER TRANSMITTER AND WIRELESS POWER TRANSCEIVER - Disclosed are a wireless power transmitter capable of transmitting power wirelessly according to an impedance of an output side and a wireless power transceiver. There are provided a wireless power transmitter and a wireless power transceiver including: a wireless power transmitting unit converting input power into a preset transmission power and transmitting the converted input power wirelessly; and a controlling unit controlling a transmission of the transmission power according to a level of output impedance of the transmission power output from the wireless power transmitting unit. | 09-27-2012 |
20120280648 | APPARATUS AND METHOD FOR CHARGING WIRELINE AND WIRELESS POWERS - Disclosed herein are an apparatus and a method for charging wireline and wireless powers. The apparatus for charging wireline and wireless powers includes: a main battery; an auxiliary battery; a wireline charging module providing wireline power to the main and auxiliary batteries; and a wireless charging module connected to the wireline charging module to thereby provide wireless power to the main and auxiliary batteries. Therefore, wireline charging and the wireless charging may be simultaneously performed, thereby making it possible to save a time required to charge power and to improve the convenience for users according to various charging scenarios using the wireline charging and the wireless charging. | 11-08-2012 |
20130050889 | WIRELESS POWER TRANSMISSION SYSTEM AND METHOD OF CONTROLLING THE SAME - Disclosed herein is a wireless power transmission system, including: a transmission unit generating and transmitting power for charging a battery; a reception unit receiving the transmitted power and charging the battery with power; and a transmission control unit detecting a charging status of the battery by using the transmitted power, and, if the charging status of the battery is in a damage section due to reflective power, controlling the transmission unit to transmit power lower than power of a normal operation, whereby damage of transmission and reception devices due to a reflective wave can be minimized. | 02-28-2013 |
20130057230 | POWER FACTOR CORRECTION CONTROL DEVICE AND ZERO-CURRENT DETECTION METHOD FOR POWER FACTOR CORRECTION CONTROL DEVICE - The present invention discloses an impedance matching apparatus. The impedance matching apparatus includes: a multilayer printed circuit board; a signal line including a plurality of signal layers with the same pitch and formed by sequentially arranging the plurality of signal layers on the multilayer printed circuit board; and a ground plane including a plurality of ground layers, wherein the plurality of ground layers are arranged to get closer to a bottom surface of the multilayer printed circuit board from a region corresponding to one side of the signal line to a region corresponding to the other side of the signal line. The impedance matching apparatus can implement a line width without any problem of a process yield by determining specific impedance by a distance between the signal layer and the ground layer formed in corresponding positions, thereby improving the process yield. | 03-07-2013 |
20130082672 | CAPACITOR-FREE LOW DROP-OUT REGULATOR - There is provided a low drop-out regulator. The low drop-out regulator includes an amplifier including an odd number of operational amplifiers connected to one another in series, and an output unit including a pass transistor operated by an output from the amplifier and generating an output voltage to be applied to a load, wherein the pass transistor is an N-channel transistor, and the amplifier controls a feedback loop gain between an output terminal of one of the odd number of operational amplifiers and the output unit. The feedback loop gain may be controlled independently from the trans-conductance of the pass transistor, whereby the stable output voltage may be generated, even in the case that the load and the input voltage are changed, and the design parameter may be simplified. | 04-04-2013 |
20140333147 | WIRELESS POWER TRANSMISSION/RECEPTION APPARATUS AND METHOD - A wireless power transmission/reception apparatus includes a wireless power transmission unit. The transmission unit is configured to generate a wireless power signal to be transmitted, transmit the wireless power signal using magnetic resonance, receive a reflected wireless power signal from a wireless power reception unit, determine whether a load device is present, and transmit a further wireless power signal when it is determined that the load device is present in such a way that impedance and output power depending on variation in a distance to the load device are tracked, and wireless power is supplied to the load device in an optimized state. Accordingly, a separate transceiver module is not provided for the purpose of performing communication between a transmitting end and a receiving end, and a reception environment is automatically detected, thus enabling wireless power to be transmitted in an optimal wireless power transmission state. | 11-13-2014 |
20160056641 | WIRELESS POWER TRANSMISSION SYSTEM AND METHOD OF CONTROLLING THE SAME - Disclosed herein is a wireless power transmission system, including: a transmission unit generating and transmitting power for charging a battery; a reception unit receiving the transmitted power and charging the battery with power; and a transmission control unit detecting a charging status of the battery by using the transmitted power, and, if the charging status of the battery is in a damage section due to reflective power, controlling the transmission unit to transmit power lower than power of a normal operation, whereby damage of transmission and reception devices due to a reflective wave can be minimized. | 02-25-2016 |
Patent application number | Description | Published |
20120119208 | SEMICONDUCTOR APPARATUS AND FABRICATING METHOD THEREOF - A semiconductor apparatus includes a semiconductor chip formed on a predetermined area of a wafer, wafer test block formed on an area outside the predetermined area, and signal line for electrically connecting the semiconductor chip to the wafer test block. Through-silicon via is formed to vertically penetrate the signal line. | 05-17-2012 |
20120274348 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via receives an input voltage. The voltage driving unit is connected to the through via to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal. | 11-01-2012 |
20120286849 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal. | 11-15-2012 |
20130094316 | MEMORY SYSTEM - A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other. | 04-18-2013 |
20140043884 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data. | 02-13-2014 |
20140048947 | SYSTEM PACKAGE - A system package includes an interposer, a control chip mounted onto the interposer, and first and second semiconductor chips mounted onto the interposer and electrically coupled to the control chip through the interposer. The first and second chips are configured to operate under the control of the control chip. The first semiconductor chip is positioned along one side of the control chip, and the second semiconductor chip is positioned along another side of the control chip. | 02-20-2014 |
Patent application number | Description | Published |
20130147134 | ACTIVE GEOMETRY CONTROL SUSPENSION SYSTEM - An active geometric control suspension system may include an upper arm connected to a side above and between a rear wheel-sided knuckle and a subframe, and an assist link connected to the other side above and between the knuckle and the subframe, together with a node-changeable unit, wherein the node-changeable unit includes a housing formed at a portion of the subframe, a track-variable kit detachably coupled to brackets of the housing, cam-operating rails fixed to a side of the track-variable kit, a cam disposed on the cam-operating rails of the track-variable kit to be slidable up/down along the cam-operating rails, and a cam bolt connecting the cam with a vehicle body-sided connecting portion of the assist link. | 06-13-2013 |
20140132007 | ENERGY REGENERATION DEVICE OF SUSPENSION SYSTEM FOR VEHICLE - An energy regeneration device of a suspension system for a vehicle includes: a suspension link that connects a wheel carrier to a vehicle body; a bush unit that outputs hinge motion of the suspension link through an output gear; a one-way power transmission mechanism that receives the hinge motion transmitted from the output gear through an input gear, and outputs only one-way rotational power; a generator that is disposed at a side of the vehicle body and generates electricity while being rotated by the transmitted one-way rotational power; a speed-up mechanism that speeds up one-way rotational power transmitted from the one-way power transmission mechanism, and transmits the one-way rotational power to a rotary shaft of the generator; a rectifier that rectifies the electricity generated by the generator; and a battery that accumulates electric energy. | 05-15-2014 |
20140183873 | ENERGY REGENERATION DEVICE OF SUSPENSION SYSTEM FOR VEHICLE - An energy regeneration device of a suspension system for a vehicle, includes a suspension link that connects a wheel carrier to a vehicle body, a bush unit that is disposed between a vehicle body connection portion of the suspension link and the vehicle body and outputs hinge motion of the suspension link through an output gear, a one-way power transmission mechanism that is connected with the output gear of the bush unit, receives the hinge motion transmitted from the output gear through an input gear, and outputs only one-way rotational power, and a generator that is disposed at a side of the vehicle body and generates electricity while being rotated by the transmitted one-way rotational power. | 07-03-2014 |
20140300067 | ACTIVE GEOMETRY CONTROL SUSPENSION SYSTEM OF VEHICLE - An active geometry control suspension system may include a toe control mechanism having an assist link disposed between the wheel carrier and the sub-frame, a housing unit integrally formed with the sub-frame and having hinge brackets integrally formed at both sides of a wheel side one surface, a guide unit configured to guide a vehicle body side connection portion of the assist link along a predetermined trajectory through a cam guider which slides upward and downward along guide, a drive unit configured to transmit rotating driving torque, and a power transmission unit configured to transmit the linear motion to the vehicle body side connection portion of the assist link so that the vehicle body side connection portion of the assist link is raised and lowered along a predetermined trajectory of the guide unit by the rotating driving torque of the screw shaft. | 10-09-2014 |
Patent application number | Description | Published |
20140370704 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LOW-K DIELECTRIC LAYER - Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges. | 12-18-2014 |
20150179582 | WIRING STRUCTURES AND METHODS OF FORMING THE SAME - A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. | 06-25-2015 |
20150194333 | Methods of Forming Wiring Structures and Methods of Fabricating Semiconductor Devices - Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns. | 07-09-2015 |
20150287682 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern. | 10-08-2015 |
20160056235 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer. | 02-25-2016 |
20160133512 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING A PLURALITY OF ETCH STOP LAYERS - A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer. | 05-12-2016 |
20160133577 | Wiring Structures and Methods of Forming the Same - A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. | 05-12-2016 |
Patent application number | Description | Published |
20130263077 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME - According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices. | 10-03-2013 |
20140077303 | FIN TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor. | 03-20-2014 |
20140097493 | CELLS INCLUDING AT LEAST ONE FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING THE SAME - A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins. | 04-10-2014 |
20150137252 | LAYOUT DESIGN SYSTEM, LAYOUT DESIGN METHOD, AND SEMICONDUCTOR DEVICE FABRICATED BY USING THE SAME - A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit. | 05-21-2015 |
20150137262 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction. | 05-21-2015 |
20150302135 | METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT - A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules. | 10-22-2015 |
20160027769 | INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE BASED ON INTEGRATED CIRCUIT, AND STANDARD CELL LIBRARY - An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts. | 01-28-2016 |
20160055283 | STANDARD CELL LIBRARY, METHOD OF USING THE SAME, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed. | 02-25-2016 |
20160055284 | Standard Cell Library and Methods of Using the Same - A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region. | 02-25-2016 |
20160055285 | METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY - Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed. | 02-25-2016 |
20160055286 | METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT - A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced. | 02-25-2016 |
20160098508 | METHOD AND SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout. | 04-07-2016 |
20160099211 | SYSTEM ON CHIP - Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact. | 04-07-2016 |
Patent application number | Description | Published |
20080243869 | INTER-HOME SHARING APPARATUS AND METHOD USING HOME NETWORK DEVICE - An inter-home content sharing apparatus and method are provided. The inter-home content sharing apparatus includes a home network protocol stack which communicates with the home network devices according to a home network protocol; a remote storage controller which receives a request for sharing content from the home network devices through the home network protocol, connects to a remote storage to upload the content, and controls the remote storage to extract metadata of the content; and a message controller which controls transception of notification messages including sharing information on the uploaded content. | 10-02-2008 |
20080256254 | COMMUNICATION METHOD AND APPARATUS USING HYPERTEXT TRANSFER PROTOCOL - A communication method for implementing a real-time streaming using hypertext transfer protocol (HTTP) in a network is provided. Chunked encoding of HTTP is applied so that information can be exchanged between a server and a client while an HTTP request is being progressed. Therefore, bidirectional communication between the client and the server using HTTP is possible without modifying an existing HTTP protocol, and real-time transmission can be implemented. | 10-16-2008 |
20090310412 | METHODS OF DATA MANAGEMENT IN NON-VOLATILE MEMORY DEVICES AND RELATED NON-VOLATILE MEMORY SYSTEMS - A data management method includes assigning data buffered in a first memory device into at least two different groups for transfer to a second memory device. At least one of the different groups has at least two units of the data assigned thereto. The data is transferred from the first memory device to the second memory device in a sequence according to a respective priority associated with each of the different groups and in group-by-group manner such that units of the data assigned to a group having a higher priority are transferred to the second memory device prior to units of the data assigned to a group having a lower priority. Related systems and methods are also discussed. | 12-17-2009 |
20100220526 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A nonvolatile memory device stores program data in a first address area, determines whether the first address area is a most significant address area and whether the program data is reliable data, and upon determining that the first address area is not a most significant address area and that the program data is reliable data, additionally stores the program data in a second address area. | 09-02-2010 |
20120102157 | COMMUNICATION METHOD AND APPARATUS USING HYPERTEXT TRANSFER PROTOCOL - A communication method for implementing a real-time streaming using hypertext transfer protocol (HTTP) in a network is provided. Chunked encoding of HTTP is applied so that information can be exchanged between a server and a client while an HTTP request is being progressed. Therefore, bidirectional communication between the client and the server using HTTP is possible without modifying an existing HTTP protocol, and real-time transmission can be implemented. | 04-26-2012 |
20140281173 | NONVOLATILE MEMORY SYSTEM, SYSTEM INCLUDING THE SAME, AND METHOD OF ADAPTIVELY ADJUSTING USER STORAGE REGION IN THE SAME - A method is for adaptively adjusting a user storage region in an entire storage region of a nonvolatile memory system. The method includes a host transmitting a user region information request command to the nonvolatile memory system, the nonvolatile memory system transmitting user region information to the host, the host changing the user region information, the host transmitting a user region information setting command to the nonvolatile memory system, and the nonvolatile memory system controlling a size of the user storage region in response to the user region information setting command. | 09-18-2014 |
20140281338 | HOST-DRIVEN GARBAGE COLLECTION - A host receives information related to garbage collection of a storage device, and it controls selective execution of garbage collection by the storage device according to the received information. | 09-18-2014 |
20140325125 | ATOMIC WRITE METHODS - A method of transmitting atomic write data from a host to a data storage device in a data system includes; communicating a header identifying a plurality of data chunks associated with an atomic write operation from the host to the data storage device and storing the header in a buffering area designated in the data storage device, then successively communicating the plurality of data chunks from the host to the data storage device and successively storing the each one of the plurality of data chunks in the buffering area, and then storing write data including at least the plurality of data chunks in a first area of storage media in the data storage device. | 10-30-2014 |
20140325126 | DATA STORAGE DEVICE PERFORMING ATOMIC WRITE AND RELATED METHOD OF OPERATION - A method of operating a data storage device comprises allocating a plurality of data blocks among received data to a plurality of intellectual property (IP) cores, performing an atomic write independently for of the IP cores, wherein the atomic write for each of the IP cores writes corresponding allocated data blocks to a corresponding memory region of the data storage device, and generating an independent identifier indicating completion of the atomic write for each of the IP cores. | 10-30-2014 |
20140325148 | DATA STORAGE DEVICES WHICH SUPPLY HOST WITH DATA PROCESSING LATENCY INFORMATION, AND RELATED DATA PROCESSING METHODS - A method is for operating a data storage device including a plurality of memory chips. The method includes generating state information regarding the plurality of memory chips, storing the generated state information in a memory, receiving an access command from a host, analyzing the state information in response to the access command, and transmitting a response to the host indicative of whether the access command is performed based on the analyzed state information. | 10-30-2014 |
20150347291 | FLASH MEMORY BASED STORAGE SYSTEM AND OPERATING METHOD - A flash memory based storage system and operating method are provided. A host of the storage system requests an erase unit size from the storage device and uses a multiple of the erase unit size to partition a logical address. Each host block may be assigned a state selected from a group of states including: an open state in which an erase unit of the storage device is allocated, a write state in which data is written at an erase unit of the storage device, a close state in which a write operation is no longer performed, and an invalidate state in which valid data of a host block is invalidated. | 12-03-2015 |
20160124740 | DATA STORAGE DEVICE AND METHOD FOR REDUCING FIRMWARE UPDATE TIME AND DATA PROCESSING SYSTEM INCLUDING THE DEVICE - A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory. | 05-05-2016 |
Patent application number | Description | Published |
20080240331 | INSPECTION APPARATUS FOR REACTOR BOTTOM MOUNTED INSTRUMENTATION NOZZLE - Provided is an inspection apparatus for a reactor BMI nozzle. The apparatus includes a motor, a ball screw, a guide, and a coil spring. The motor is installed at a transmission of a bracket provided under a quick connector of an ROSA-V six-axis system and enables vertical driving of an inspection probe. The ball screw converts a rotary motion of the motor into a vertical motion and vertically reciprocating the inspection probe. The guide compels an axial arrangement of the inspection probe and removes eccentricity generated when the inspection probe is inserted into the nozzle. The coil spring is installed above the guide and prevents an impact propagation of an instrument. | 10-02-2008 |
20100011522 | APPARATUS FOR VISUALLY INSPECTING AND REMOVING FOREIGN SUBSTANCE FROM GAP OF HEAT TUBE BUNDLE IN UPPER PART OF TUBE SHEET OF SECOND SIDE OF STEAM GENERATOR - An apparatus that visually inspects a state of sludge and a foreign substance between steam generator bundles positioned at an upper part of a tube sheet of a second side of a steam generator of a nuclear power plant (Korean standard type) using a visual inspector mounted in a robot moving on an inner wall surface of the steam generator and that removes a foreign substance with a foreign substance remover when the foreign substance is found are provided. The apparatus for visually inspecting and removing a foreign substance from a gap of a heat tube bundle in an upper part of a tube sheet of a second side of a steam generator, including: a robot including a transfer unit that moves on a wall surface within a ring of the steam generator, a lift that is provided in the transfer unit to vertically move upward and downward, a visual inspector that is rotatably provided in the lift, and that moves upward and downward by driving the lift, and that monitors sludge or a foreign substance injected into a gap of the heat tube, and a foreign substance remover that is provided at one side of the visual inspector and that removes the sludge or the foreign substance existing in the gap of the heat tube; a controller that is provided at one side of the steam generator and that controls the robot on the spot; a remote controller that is provided at the outside, and that is connected to the controller through a wire, and that controls the robot; and an encoder mounting fixture that is fixed to one side of a handhole of the steam generator, and that is connected to the controller through a first cable, and that receives and supplies a second cable connected to the robot. | 01-21-2010 |
20100122592 | SYSTEM FOR MEASURING DEFLECTION OF ROTATING SHAFT IN WIRELESS MANNER - Disclosed herein is a system for measuring the deflection of a rotating shaft in a wireless manner. The system includes a non-contact-type angle division device, a plurality of wireless contact-type displacement sensors, a plurality of wireless transmitters, a relay, and a data reader. The non-contact-type angle division device is placed on a vertical rotating shaft and measures and transmits the angle of rotation of the rotating shaft. The wireless contact-type displacement sensors are installed on the outer circumferential surface of the rotating shaft, and measure the strain of the rotating shaft. The wireless transmitters transmit data about the displacement of the rotating shaft measured by the wireless contact-type displacement sensor. The relay receives and relays transmission signals from the non-contact-type angle division device and the wireless transmitters. The data reader receives the transmission signals from the relay, and performs simulation reading. | 05-20-2010 |
20110118548 | ARC-SHAPED FLEXIBLE PRINTED CIRCUIT FILM TYPE ENDOSCOPE USING IMAGING DEVICE WITH DRIVING HOLES - Disclosed herein is an arc-shaped flexible printed circuit film type endoscope using an imaging device with driving holes. The endoscope has an image photographing means and an object insertion means. The endoscope includes a plurality of driving holes which are formed at regular intervals in a longitudinal direction of the object insertion means, and a driving means which rotates while being sequentially inserted into the driving holes, thus moving the object insertion means. The endoscope precisely controls a movement into a small space, makes it easy to inspect a narrow heat transfer tube or gaps formed between heat transfer tubes, achieves high economic efficiency, increases the reliability of endoscopy, and increases a life-span. | 05-19-2011 |
20140150228 | MACHINING, EXAMINATION, AND WELDING INTEGRAL DEVICE FOR NOZZLE - The present invention relates to a machining, examination, and welding integral device for a nozzle, and more particularly, to a machining, examination, and welding integral device for a nozzle in which machining, examination, and welding can be made in the nozzle by one device. To this end, there is provided a machining, examination, and welding integral device for a nozzle including: a pair of caps provided to be separated from each other; a welding unit provided between the pair of caps to weld a junction part of the nozzle and a pipe; a examination unit coupled to one side of the welding unit to check whether the junction part is defective; and a machining unit coupled to the top of the welding unit to remove the surface of a welded portion of the junction part and/or process the welded portion of the junction part. | 06-05-2014 |
Patent application number | Description | Published |
20140132468 | DIPOLE ANTENNA MODULE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A dipole antenna module and an electronic apparatus include an antenna element, a power feeder formed at an end of the antenna element and connected to a circuit board to process an antenna signal through a cable, and a ground part to ground a ground of the cable such that the ground part keeps a preset gap from the antenna element and is grounded to a conductor of the circuit board. | 05-15-2014 |
20140176370 | ANTENNA, ELECTRONIC APPARATUS WITH THE SAME, AND ANTENNA MANUFACTURING METHOD - An antenna includes a sintered body block with a predetermined magnetic permeability or a predetermined dielectric constant, the sintered body block having at least one air cavity; and an antenna pattern formed on a surface of the sintered body block. | 06-26-2014 |
20140218250 | CASE AND ELECTRONIC APPARATUS - An electronic apparatus includes a metallic case including an antenna pattern formed on an area of the metallic case where two sides surfaces of the case meet, the antenna pattern forming a slit antenna including a slit connecting one side of the antenna pattern to an open area of the metallic case, and a circuit board configured to process signals received at the antenna pattern. | 08-07-2014 |
20160064804 | ANTENNA DEVICE AND ELECTRONIC DEVICE INCLUDING SAME - An antenna device implemented to prevent the deterioration in radiation performance due to a metal mechanical part and an electronic device including the same is provided. The electronic device includes a metal member in a shape of a loop that is disposed in at least one area of the electronic device and a substrate (printed circuit board (PCB)) for supplying power to a preset location of the metal member in order to use the metal member as an antenna radiator, wherein at least one location of the metal member that differs from the power-supplied location is grounded through the substrate. | 03-03-2016 |
20160124396 | ANTENNA APPARATUS AND ELECTRONIC DEVICE HAVING THE SAME - An electronic device is provided. The electronic device includes a housing comprising a recess portion formed along an edge of the housing, a sealing member arranged in the recess portion, so as to provide a seal between structures coupled with the housing, an antenna member disposed in at least a portion of the sealing member, and a substrate electrically connected with the antenna member. | 05-05-2016 |
Patent application number | Description | Published |
20100120209 | ETCHANT COMPOSITION, AND METHOD OF FABRICATING METAL PATTERN AND THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - An etchant composition is provided. The etchant composition includes about 40 to about 65 wt % of phosphoric acid, about 2 to about 5 wt % of nitric acid, about 2 to about 20 wt % of acetic acid, about 0.1 to about 2 wt % of a compound containing phosphate, about 0.1 to about 2 wt % of a compound simultaneously containing an amino group and a carboxyl group, and a remaining weight percent of water for the total weight of the composition. | 05-13-2010 |
20110183476 | ETCHING SOLUTION COMPOSITION AND METHOD OF ETCHING USING THE SAME - An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH | 07-28-2011 |
20120153287 | ETCHANT, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE SAME - An etchant includes: 5 to 20 wt % of persulfate, 1 to 10 wt % of at least one compound of an inorganic acid, an inorganic acid salt, or a mixture thereof, 0.3 to 5 wt % of a cyclic amine compound, 1 to 10 wt % of at least one compound of an organic acid, an organic acid salt, or a mixture thereof, 0.1 to 5 wt % of p-toluenesulfonic acid, and water, based on the total weight of the etchant. A copper-titanium etchant further includes 0.01 to 2 wt % of a fluoride-containing compound. A method of forming a display device using the etchant, and a display device, are also disclosed. | 06-21-2012 |
20120208310 | NON-HALOGENATED ETCHANT AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE NON-HALOGENATED ETCHANT - Exemplary embodiments of the present invention disclose a non-halogenated etchant for etching an indium oxide layer and a method of manufacturing a display substrate using the non-halogenated etchant, the non-halogenated etchant including nitric acid, sulfuric acid, a corrosion inhibitor including ammonium, a cyclic amine-based compound, and water. | 08-16-2012 |
20120252148 | ECHTANT AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE SAME - An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water. | 10-04-2012 |
20130115727 | ETCHING COMPOSITION AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SYSTEM - An etching composition and a method of manufacturing a display substrate using the etching composition are disclosed. The etching composition includes phosphoric acid (H | 05-09-2013 |
20130178023 | ETCHING SOLUTION COMPOSITION AND METHOD OF ETCHING USING THE SAME - An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH | 07-11-2013 |
20140024206 | ETCHANT COMPOSITION AND METHOD OF FORMING METAL WIRE AND THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - A etchant composition that includes, based on a total weight of the etchant composition, about 0.5 wt % to about 20 wt % of a persulfate, about 0.5 wt % to about 0.9 wt % of an ammonium fluoride, about 1 wt % to about 10 wt % of an inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 10.0 wt % of a sulfonic acid, about 5 wt % to about 10 wt % of an organic acid or a salt thereof, and a remainder of water. The etchant composition may be configured to etch a metal layer including copper and titanium, to form a metal wire that may be included in a thin film transistor array panel of a display device. | 01-23-2014 |
20140295599 | ETCHANT, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE SAME - An etchant includes: 5 to 20 wt % of persulfate, 1 to 10 wt % of at least one compound of an inorganic acid, an inorganic acid salt, or a mixture thereof, 0.3 to 5 wt % of a cyclic amine compound, 1 to 10 wt % of at least one compound of an organic acid, an organic acid salt, or a mixture thereof, 0.1 to 5 wt % of p-toluenesulfonic acid, and water, based on the total weight of the etchant. A copper-titanium etchant further includes 0.01 to 2 wt % of a fluoride-containing compound. A method of forming a display device using the etchant, and a display device, are also disclosed. | 10-02-2014 |
20150259598 | ETCHANT COMPOSITION AND METHOD OF FORMING METAL WIRE AND THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - A etchant composition that includes, based on a total weight of the etchant composition, about 0.5 wt % to about 20 wt % of a persulfate, about 0.5 wt % to about 0.9 wt % of an ammonium fluoride, about 1 wt % to about 10 wt % of an inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 10.0 wt % of a sulfonic acid, about 5 wt % to about 10 wt % of an organic acid or a salt thereof, and a remainder of water. The etchant composition may be configured to etch a metal layer including copper and titanium, to form a metal wire that may be included in a thin film transistor array panel of a display device. | 09-17-2015 |
Patent application number | Description | Published |
20110103737 | OPTICAL WIRING BOARD AND MANUFACTURING METHOD THEREOF - An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a base substrate having a wiring groove formed therein, forming a first clad layer by filling a first clad substance in the wiring groove, stacking an intermediate insulating layer on the base substrate, in which the intermediate insulating layer has a through-hole formed therein and the through-hole corresponds to the wiring groove, forming a core unit on the first clad layer, forming a second clad layer by filling a second clad substance in the through-hole, in which the second clad layer covers the core unit, and stacking a cover insulting layer on the intermediate insulating layer, in which the cover insulating layer covers the second clad layer. | 05-05-2011 |
20110116736 | OPTICAL WIRING BOARD AND MANUFACTURING METHOD THEREOF - An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a base substrate having an optical waveguide layer with a mirror groove formed on one surface thereof and a first insulation layer stacked on one surface of the optical waveguide layer and having a through-hole connected with the mirror groove formed thereon, forming a metal mirror layer connected from the mirror groove to an inner wall of the through-hole and forming an electrode pad on a side of the other surface of the optical waveguide layer, in which the electrode pad is disposed in accordance with the position of the metal mirror layer. | 05-19-2011 |
20110116737 | OPTICAL WIRING BOARD AND MANUFACTURING METHOD THEREOF - An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a flexible optical waveguide layer, selectively forming a reinforcing clad on one surface of the optical waveguide layer and forming a mirror groove on the other surface of the optical waveguide layer in accordance with where the reinforcing clad is formed. Thus, the clad can be formed thick only on the place where the mirror groove is to be formed, and thus a flexible optical wiring board having flexibility can be manufactured even though the optical wiring board is generally made thin. | 05-19-2011 |
20110168666 | MANUFACTURING METHOD FOR OPTICAL WAVEGUIDE - A method of manufacturing an optical waveguide is disclosed. The method in accordance with an embodiment of the present invention includes providing a carrier, fixing a base substrate to the carrier by using a first insulation layer such that the base substrate is directly stacked on the carrier, stacking an optical waveguide layer on at least one of the base substrate and the first insulation layer, and severing the base substrate such that the base substrate and the optical waveguide layer are separated from the carrier. Accordingly, the optical waveguide layer can be formed with a uniform thickness since wrinkles in the base substrate supporting the optical waveguide layer are prevented from forming during the manufacturing process. | 07-14-2011 |
Patent application number | Description | Published |
20120091515 | Semiconductor Devices Having Backside Illuminated Image Sensors - A semiconductor substrate includes a photodiode on a support substrate. An insulating layer is provided between the support substrate and the semiconductor substrate. A first conductive pattern is provided in the insulating layer. A first through electrode penetrates the support substrate to be in contact with the first conductive pattern. | 04-19-2012 |
20120313208 | IMAGE SENSOR AND METHOD OF FORMING THE SAME - An image sensor and a method of forming the same, where the image sensor may include a substrate including a pixel region and a pad region, a through via configured to penetrate the substrate in the pad region, a plurality of unit pixels in the pixel region, and a light shielding pattern between the plurality of unit pixels. The through via and the light shielding pattern include a same material. | 12-13-2012 |
20130017646 | METHOD OF MANUFACTURING IMAGE SENSOR HAVING BACKSIDE ILLUMINATION STRUCTUREAANM KIM; Sang-hoonAACI Seongnam-siAACO KRAAGP KIM; Sang-hoon Seongnam-si KRAANM PARK; Byung-junAACI Yongin-siAACO KRAAGP PARK; Byung-jun Yongin-si KRAANM AN; Hee-chulAACI Yongin-siAACO KRAAGP AN; Hee-chul Yongin-si KR - A method of manufacturing an image sensor having a backside illumination (BSI) structure includes forming a wiring unit on a front side of a semiconductor substrate, forming an anti-reflective layer in an active pixel sensor (APS) region on a back side of the semiconductor substrate, a photodiode being between the back and front sides of the semiconductor substrate, forming an etch stopping layer on the anti-reflective layer, forming an interlayer insulating layer on the etch stopping layer, the interlayer insulating layer having an etch selectivity with respect to the etch stopping layer, and etching the interlayer insulating layer in the APS region using the etch stopping layer as an etch stopping point. | 01-17-2013 |
20130221465 | IMAGE SENSORS - Image sensors include a first insulation interlayer structure on a first surface of a substrate and having a multi-layered structure. A first wiring structure is in the first insulation interlayer structure. A via contact plug extends from a second surface of the substrate and penetrates the substrate to be electrically connected to the first wiring structure. Color filters and micro lenses are stacked on the second surface in a first region of the substrate. A second insulation interlayer structure is on the second surface in a second region of the substrate. A second wiring structure is in the second insulation interlayer structure to be electrically connected to the via contact plug. A pad pattern is electrically connected to the second wiring structure and having an upper surface through which an external electrical signal is applied. Photodiodes are between the first and second wiring structures in the first region. | 08-29-2013 |
20140239362 | IMAGE SENSOR AND METHOD OF FORMING THE SAME - An image sensor includes a substrate having a first surface opposing a second surface and a plurality of pixel regions. A photoelectric converter is included in each of the pixel regions, and a gate electrode is formed on the photoelectric converter. Also, a pixel isolation region isolates adjacent pixel regions. The pixel isolation region includes a first isolation layer coupled to a channel stop region. The channel stop region may include an impurity-doped region. | 08-28-2014 |
20140249426 | Probe for Diagnosing Otitis Media Using Terahertz Waves and Otitis Media Diagnosis System and Method - The present invention relates to a otitis media diagnosis system using terahertz electromagnetic waves, which can diagnose otitis media using terahertz electromagnetic waves in a non-invasive manner, and which can accurately diagnose otitis media by acquiring images on the tympanic cavity using terahertz electromagnetic waves with excellent transmittance, and which can quickly and accurately divide exudative otitis media and suppurative otitis media using terahertz electromagnetic waves that are sensitive to moisture, and which is safe to a body using terahertz electromagnetic waves. The otitis media diagnosis system includes a terahertz probe including a generating unit for radiating terahertz electromagnetic waves from the outside of an ear toward a tympanic cavity and a detection unit for detecting the reflected terahertz electromagnetic waves reflected from the tympanic cavity. | 09-04-2014 |
Patent application number | Description | Published |
20100091602 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output converted addresses such that only one address bit of the converted addresses with respect to the previous converted addresses are toggled to output the converted addresses. The converted addresses output form the code conversion unit do not overlap with one another. | 04-15-2010 |
20110001552 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse. | 01-06-2011 |
20110001559 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data. | 01-06-2011 |
20110006391 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units. | 01-13-2011 |
20110161581 | SEMICONDUCTOR CIRCUIT APPARATUS - A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank. | 06-30-2011 |
20120092062 | SEMICONDUCTOR SYSTEM - A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information. | 04-19-2012 |
20120155200 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory device. | 06-21-2012 |
20120217654 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a wafer comprising a chip that passes a test and a chip that does not pass a test, one or more first stacked chips that are stacked over the chip that passes a test, and one or more second stacked chips that are stacked over the chip that does not pass a test, wherein the second stacked chips comprise at least one between an chip that does not pass a test and a dummy chip. | 08-30-2012 |
20120266034 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section. | 10-18-2012 |
20120269018 | MEMORY SYSTEM HAVING MEMORY AND MEMORY CONTROLLER AND OPERATION METHOD THEREOF - An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory. | 10-25-2012 |
20130214389 | INTEGRATED CIRCUIT - An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip. | 08-22-2013 |
20140291855 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon via, and suitable for buffering the signal, an internal circuit, and a delay compensation block suitable for applying delay corresponding to the buffering blocks of the chips to the signal, wherein the delay compensation blocks of the chips compensates for delay difference of the signal transferred to and from the internal circuit of the chip, due to operations of the buffering block, based on stack information for distinguishing the chips. | 10-02-2014 |
20150060854 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a main region suitable for performing a first test operation and a second test operation respectively based on a first test signal and a second test signal in a test mode, a first test region electrically connected to the main region and suitable for generating and transferring the first test signal to the main region in the test mode, and a second test region electrically connected to the main region or the first test region with a scribe lane disposed therebetween and suitable for generating and transferring the second test signal to the main region in the test mode. | 03-05-2015 |
20150098281 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal. | 04-09-2015 |
20150112072 | PROCESS OF PREPARING SOLIFENACIN OR SALT THEREOF, AND NOVEL INTERMEDIATE USED IN THE PROCESS - Disclosed herein is a method of preparing solifenacin or a salt thereof, including the steps of: (a) reacting (R)-quinuclidinol with bis(pentafluorophenyl)carbonate in an organic solvent to prepare a solifenacin intermediate, (3R)-1-azabicyclo[2,2,2]oct-3-yl pentafluorophenylcarbonate, and (b) reacting the solifenacin intermediate with (1S)-1-phenyl-1,2,3,4-tetrahydroisoquinoline in an organic solvent to prepare solifenacin. The method is advantageous in that high-purity solifenacin or a salt thereof can be simply and efficiently prepared with high yield using a novel intermediate. | 04-23-2015 |
20160048425 | MEMORY DEVICE HAVING A SHAREABLE ERROR CORRECTION CODE CELL ARRAY - A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array. | 02-18-2016 |
Patent application number | Description | Published |
20100110260 | DEVICE AND METHOD FOR RECORDING AND RECONSTRUCTING DIGITAL HOLOGRAM WITHOUT VIRTUAL IMAGE - The present invention relates to a device and method for digital hologram recording and reconstructing that solves the problem of overlapping real and virtual images when reconstructing a hologram with a digital hologram device such as a digital hologram microscope. The device comprises a hologram reconstructing module for dividing the hologram area recorded on the CCD, recording in the interim each divided area whereby for each of the areas the pixel values of the rest of the areas except for that divided area is set to zero, outputting a reconstructed image with the virtual image removed by integrating each of the reconstructed hologram images recorded in the interim, and a control unit for controlling the hologram recording on the CCD, including dividing, mid-recording, and integration operations of the hologram reconstructing module, thus leading to perfect holographic information of the object. | 05-06-2010 |
20140318925 | MEDIUM HANDLING APPARATUS AND FINANCIAL DEVICE - Provided is a medium handling apparatus. The medium handling apparatus comprises a guider to define a first space in which a medium to be deposited and a medium to be withdrawn are handled and a second space in which a rejected medium is handled and at least one pick-up roller to pick up the medium that is disposed in each of the first and second spaces. | 10-30-2014 |
20150190119 | ULTRASOUND DIAGNOSTIC APPARATUS AND METHOD OF OPERATING THE SAME - Disclosed are an ultrasound diagnostic apparatus and a method of operating the same. The method includes transmitting an ultrasound signal to an object to receive an echo signal corresponding to the ultrasound signal from the object, generating an ultrasound image, based on the received echo signal, detecting cross-sectional information indicating which cross-sectional surface of the object the generated ultrasound image shows, and displaying the ultrasound image and a cross-sectional information image corresponding to the detected cross-sectional information. | 07-09-2015 |
20150302604 | MEDICAL IMAGING APPARATUS AND METHOD OF OPERATING THE SAME - A medical imaging apparatus and a method of operating the same are provided. The method includes acquiring three-dimensional (3D) volume data about an object, generating a 3D image based on the 3D volume data, extracting a muscle tissue figure corresponding to a muscle tissue shape of the object by grouping voxels included in the 3D image, analyzing a motion of the object based on the extracted muscle tissue figure, and displaying the extracted muscle tissue figure and a result of the analysis. | 10-22-2015 |
20160032622 | MORTISE LOCK - Disclosed herein is a mortise lock which can open a door when a user pushes or pulls a knob. The mortise lock includes: a knob configured to be pushed and pulled by a user; a rose which is mounted at one side of the front face and the rear face of the door and to which one side of the knob is inserted and fixed in such a manner that the knob can be rotated; a gear guide to which one side of the knob inserted into the rose is connected and which is configured to vertically slide according to rotation of the knob; and a latch actuating part of which one side is connected with the gear guide and of which the other side is connected with the latch so as to be moved in a specific direction by the vertical sliding of the gear guide, wherein when the latch actuating part is moved in the specific direction, the latch is inserted or protrudes out. The mortise lock can easily open the door just by the user's one-step action to push or pull the knob indoors or outdoors. | 02-04-2016 |