Patent application number | Description | Published |
20110252245 | POWER SCALING MODULE AND POWER SCALING UNIT OF AN ELECTRONIC SYSTEM - A power scaling unit (PSU) of an electronic system is provided. The PSU includes a software programming interface (SPI) and a PSM. The SPI receives a transaction through software programming. The PSM receives the transaction from the SPI and controls a power driving element (PDE) of the electronic system to change an output of the PDE provided to a function unit of the electronic system according to the transaction. The output of the PDE is an operating voltage or an operating clock signal of the function unit. The transaction includes a command defining a power scaling operation to be performed by the PSM, a parameter used by the operation, and an event mask specifying an event which triggers the operation. | 10-13-2011 |
20120166739 | MEMORY MODULE AND METHOD FOR ATOMIC OPERATIONS IN A MULTI-LEVEL MEMORY STRUCTURE - A memory module and a corresponding method for handling atomic operations in a multi-level memory system (MLMS) are provided. The memory module receives load and store operations of the atomic operations from a data processing engine (DPE) or an upper level memory module (ULMM). The memory module logs the load operation and/or forward the load operation to a lower level memory module (LLMM) according to predetermined conditions such as cacheability or whether there is a data hit or not. In addition, the memory module executes the store operation, inhibits the store operation, or forwards the store operation to an LLMM according to predetermined conditions such as cacheability, data hit, or whether there is a matching load operation logged in the memory module. The memory module and the method ensure correct, consistent and efficient execution of atomic operations for all DPEs sharing the MLMS. | 06-28-2012 |
20130138847 | BUS APPARATUS WITH DEFAULT SPECULATIVE TRANSACTIONS AND NON-SPECULATIVE EXTENSION - A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal. | 05-30-2013 |
20130138921 | DE-COUPLED CO-PROCESSOR INTERFACE - A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP. | 05-30-2013 |
20140101352 | INTERRUPT CONTROLLER, APPARATUS INCLUDING INTERRUPT CONTROLLER, AND CORRESPONDING METHODS FOR PROCESSING INTERRUPT REQUEST EVENT(S) IN SYSTEM INCLUDING PROCESSOR(S) - An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor. | 04-10-2014 |
20140223051 | INFORMATION COLLECTION SYSTEM - An information collection system is provided. The information collection system includes an information collection unit, an information initiation unit, and an information relay unit. The information collection unit includes at least one slave port, and the information collection unit responds a transaction through the slave port. The information initiation unit includes at least one master port, and the information initiation unit initiates the transaction through the master port. The information relay unit includes at least one master port and at least one slave port, and the information relay unit relays the transaction through the master port and the slave port wherein the transaction includes a write transaction. Wherein, during an identification phase, the master port of the information initiation unit delivers a header, and the slave port of the information collection unit accepts the transaction according to the header. | 08-07-2014 |
20140366131 | SECURE BUS SYSTEM - The invention discloses a secure bus system and a bus system security method. The secure bus system includes a bus interconnect structure, a bus master, a bus device and a security control module. The security control module determines a device security attribute for the bus device. When the master security attribute of the bus master or the device security attribute of the bus device has changed, the security control module determines a security permission flag related to the bus master. When the security control module receives a bus transaction from the bus master, the security control module determines whether a security violation condition happens between the bus master and the bus device according to the security permission flag. If the security violation condition happens, the security control module triggers a security violation handling process to further restrict accessibility of the bus master to the bus device. | 12-11-2014 |
20150020211 | SECURE PROTECTION METHOD AND PROCESSOR - A secure protection method executed by a processor is provided. The secure protection method includes the following steps. Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE). Ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor. | 01-15-2015 |
20150095978 | METHOD AND APPARATUS FOR SOFTWARE-HARDWARE AUTHENTICATION OF ELECTRONIC APPARATUS - The present invention discloses a method for software-hardware authentication of an electronic apparatus includes receiving a challenge string (CS) from the electronic apparatus through a challenge string input port (CSIP). The challenge string is a string of trace data generated according to some operations of software running on the electronic apparatus. An authentication result for use in an authentication process for the software to authenticate a hardware unit of the electronic apparatus or for the hardware unit to authenticate the software is generated according to the string of the trace data. The authentication process is performed according to the generated authentication result. | 04-02-2015 |
20150293862 | HARDWARE CONFIGURATION APPARATUS - A hardware configuration apparatus is provided. The hardware configuration apparatus is a part of a hardware system and the hardware system includes at least one function. The hardware configuration apparatus includes an interface unit, a resolution unit, and an output generation unit. For each function of the hardware system, the resolution unit generates a current setting corresponding to the function based on a default setting corresponding to the function and function settings of a plurality of secure configuration entries (SCEs) corresponding to the function. The interface unit is coupled to the resolution unit and a storage storing the SCEs. The interface unit provides the SCEs to the resolution unit. The output generation unit is coupled to the resolution unit. For each function of the hardware system, the output generation unit outputs a configuration signal to enable or disable the function according to the current setting corresponding to the function. | 10-15-2015 |
20160110203 | COMPUTER SYSTEM FOR NOTIFYING SIGNAL CHANGE EVENT THROUGH CACHE STASHING - A computer system includes a cache unit and a first processing unit. The first processing unit runs a first program thread, and performs an instruction to store information of a signal change event into the cache unit through a cache stashing operation, where the signal change event is initiated by the first program thread for alerting a second program thread. | 04-21-2016 |
Patent application number | Description | Published |
20120105366 | POSITIONING ALGORITHM FOR EDGE PORTION OF TOUCH PANEL AND POSITIONING SYSTEM USING THE SAME - A positioning algorithm for edge portion of touch panel is provided. Dummy sensing lines surrounding a touch panel are provided. The x-axis and y-axis coordinate ranges of x-axis and y-axis sensing lines of the touch panel are determined. When the touch panel is touched, an x-axis sensing line, a y-axis sensing line, and a dummy sensing capacitance generated by the dummy sensing lines are located. Whether the corresponding x-axis sensing capacitance of the x-axis sensing line is smaller than or equal to the x-axis dummy sensing capacitance is determined. If so, an x-axis coordinate value is obtained according to the x-axis sensing capacitance and the dummy sensing capacitance. Whether the corresponding y-axis sensing capacitance of the y-axis sensing line is smaller than or equal to y-axis dummy sensing capacitance is determined. If so, a y-axis coordinate value is obtained according to the y-axis sensing capacitance and the dummy sensing capacitance. | 05-03-2012 |
20120113045 | TOUCH CONTROLLER FOR TOUCH-SENSING DISPLAY APPARATUS AND DRIVING METHOD THEREOF - A driving method adapted to a touch-sensing display apparatus is provided. The touch-sensing display apparatus includes a display panel and a touch panel. The driving method includes following steps. I scan signals are sequentially sent to drive the display panel to receive a plurality of data signals. M driving signals are sequentially sent to drive the touch panel to generate a plurality of sensing signals during a sensing period. The m | 05-10-2012 |
20120146927 | METHOD FOR DETECTING SINGLE-FINGER ROTATE GESTURE AND THE GESTURE DETECTING CIRCUIT THEREOF - A method for detecting a single-finger rotation gesture and a gesture detecting circuit thereof are provided. The gesture detecting circuit comprises a quadrant dividing unit, a register, a control unit, a comparing unit, and an outputting unit. The quadrant dividing unit, according to the center point, divides a touch panel into at least three quadrants and sets a plurality of data codes respectively corresponding to the quadrants. Within a predetermined time, the control unit controls the register to sequentially record the data codes respectively corresponding to the touched quadrants. When the predetermined time is reached, the comparing unit compares to judge whether the temporary data buffered in the register is the same with the default data. If the temporary data is the same with the default data, then the outputting unit outputs a rotation gesture signal. | 06-14-2012 |
20120162100 | Click Gesture Determination Method, Touch Control Chip, Touch Control System and Computer System - Disclosed is a click gesture determination method for a touch control chip capable of simply and flexibly determining a single click gesture. The click gesture determination method includes steps of comparing one or more signal values of one or more detecting signals with one or more threshold values, to determine whether a touch event occurs, continuing the above comparing if a touch event occurs, to detect a continuous occurrence time of the touch event, and comparing the continuous occurrence time with a first predefined time, and determining that a single click gesture occurs for a result of the comparison that the continuous occurrence time is longer than the first predefined time. | 06-28-2012 |
20120194445 | Moving Point Gesture Determination method, Touch Control Chip, Touch Control System and Computer System - A moving point gesture determination method is disclosed for a touch sense device mapped to a screen according to absolute position. The moving point gesture determination method includes steps of comparing one or more signal values of one or more detecting signals generated by the touch sense device with one or more threshold values, to determine whether any touch event occurs, and determining that a moving point gesture occurs once the determination indicates that a touch event occurs. | 08-02-2012 |
20120249442 | DRIVING METHOD FOR TOUCH-SENSING DISPLAY DEVICE AND TOUCH-SENSING DEVICE THEREOF - A driving method adapted to a touch-sensing display device is provided. The touch-sensing display device includes a display panel and a touch panel. The driving method includes following steps. A plurality of first scan signals of the touch panel are sequentially received, so that a plurality of first data values are obtained. It is determined whether the first data values are less than a difference between a baseline value and a threshold value. When one of the first data values is less than the difference between the baseline value and the threshold value, reporting of a touch coordinate of the touch panel is terminated. Furthermore, a touch-sensing device is also provided. | 10-04-2012 |
20120262414 | LAYOUT STRUCTURE OF CAPACITIVE TOUCH PANEL - A layout structure of a capacitive touch panel is provided. The layout structure includes a plurality of electrical paths and a plurality of touch units. The touch units respectively include at least a receiving electrode and at least a driving electrode insulated from the receiving electrode. The receiving electrodes and the driving electrodes are disposed in the same conducting layer. The receiving electrodes are connected to a controller via different electrical paths. The driving electrodes electrically are connected to each other. | 10-18-2012 |
Patent application number | Description | Published |
20090068518 | PASSIVE FUEL CELL SYSTEM - A passive fuel cell system including at least one cell unit, an anode fuel supplying unit, a cathode fuel supplying unit, and a heat-conductive material layer is provided. The cell unit includes a cathode current collector, an anode current collector, and a membrane electrode assembly disposed between them. The anode fuel supplying unit is disposed on a side of the anode current collector, and the cathode fuel supplying unit is disposed on a side of the cathode current collector. The heat-conductive material layer is disposed between the cathode current collector and the cathode fuel supplying unit and/or between the anode current collector and the anode fuel supplying unit. And, a portion of the heat-conductive material layer extends to the outside of a cell system reaction area defined by the cell unit, the anode fuel supplying unit, and the cathode fuel supplying unit along a direction parallel to the cell unit. | 03-12-2009 |
20090134879 | METHOD OF MEASURING CONCENTRATION OF FUEL - A method of measuring concentration of a fuel is provided. First, a fuel cell unit having at least an anode, a cathode, and a membrane electrode assembly (MEA) is provided. Next, a fuel is supplied to the anode, while a reactive gas is supplied to the cathode. Then, the amount of the reactive gas supplied to the cathode is adjusted and the concentration of the fuel is estimated in accordance with the consumption rate of the reactive gas in the fuel cell unit. | 05-28-2009 |
20090136792 | METHOD OF MEASURING CONCENTRATION OF FUEL - A method of measuring concentration of a fuel is provided. First, a fuel cell unit having at least an anode, a cathode, and a membrane electrode assembly (MEA) is provided. Next, a fuel is supplied to the anode, while a reactive gas is supplied to the cathode. Then, the amount of the reactive gas supplied to the cathode is adjusted and the concentration of the fuel is estimated in accordance with the consumption rate of the reactive gas in the fuel cell unit, wherein a method of estimating the concentration of the fuel in accordance with a consumption rate of the reactive gas in the cathode includes measuring a concentration of the reactive gas supplied to the cathode and estimating the concentration of the fuel in accordance with a relationship between the concentration of the reactive gas supplied to the cathode and time. | 05-28-2009 |
20100055515 | FUEL SUPPLY CONTROL METHOD AND SYSTEM FOR FUEL CELLS - An embodiment of the invention provides a fuel supply control system to control a fuel cell system to work in a predetermined temperature range by controlling a fuel supply rate. The fuel supply control system includes a fuel supply controller and a fuel supply device. The fuel supply controller calculates a temperature variation slope to generate a first fuel supply rate by increasing or decreasing the predetermined fuel supply rate according to the relationship of system temperature and predetermined working temperature, and controls a fuel delivering rate of the fuel supply device according to the first fuel supply rate. | 03-04-2010 |
20100068584 | FLAT FUEL CELL ASSEMBLY - A flat fuel cell assembly including a MEA, a cathode porous current collector, an anode porous current collector, a gas barrier material layer, a case, and at least one air baffle is provided. The cathode porous current collector and the anode porous current collector are disposed at two opposite sides of the MEA. The gas barrier material layer is disposed at a side of the cathode porous current collector and has at least one opening for exposing a surface of the cathode porous current collector. The case is disposed at a side of the MEA, the gas barrier material layer is disposed between the case and the MEA, and an air channel is located between the gas barrier material layer and the case. Additionally, the air baffle disposed within the air channel. | 03-18-2010 |
20100136697 | APPARATUS AND METHOD OF MEASURING CONCENTRATION OF FUEL - An apparatus of measuring concentration of fuel including a catalyst layer, a diffusion layer, a fuel chamber, a reactive gas chamber, and a sensor is provided. The diffusion layer is connected to the catalyst layer. The fuel chamber is suitable for containing a fuel. The diffusion layer is between the fuel chamber and the catalyst layer. The reactive gas chamber is suitable for containing a reactive gas. The catalyst layer is between the reactive gas chamber and the diffusion layer. The fuel diffuses to the catalyst layer via the diffusion layer such that a combustion reaction of the fuel and the reactive gas is conducted in the catalyst layer to consume the reactive gas and generate a gaseous product. The sensor is disposed on the reactive gas chamber for measuring the concentration of the reactive gas or the concentration of the gaseous product in the reactive gas chamber. | 06-03-2010 |
20100159299 | PASSIVE FUEL CELL ASSEMBLY - A passive fuel cell assembly including a membrane electrode assembly, an anode current collector, a cathode current collector, a hydrophilic and gas-impermeable layer, and a gas-liquid separation layer is provided. The anode current collector and the cathode current collector are disposed at two opposite sides of the membrane electrode assembly. The hydrophilic and gas-impermeable layer is disposed on the anode current collector. The gas-liquid separation layer is disposed on the hydrophilic and gas-impermeable layer, such that the hydrophilic and gas-impermeable layer is disposed between the gas-liquid separation layer and the anode current collector. | 06-24-2010 |
20120133331 | METHOD FOR CHECKING AND MODULATING BATTERY CAPACITY AND POWER BASED ON DISCHARGING/CHARGING CHARACTERISTICS - A method for checking and modulating battery capacity and power based on charging/discharging characteristics is provided. In terms of discharge, a relationship between an open circuit voltage and an output electric capacity of a battery is measured to obtain a first characteristic curve. A relationship between a voltage and the output electric capacity of a battery at a predetermined maximum charge/discharge current rate is measured to obtain a second characteristic curve. A characteristic boundary line passing the first and the second characteristic points respectively selected from the first and the second characteristic curves is established. A voltage value corresponding to the first characteristic point is higher than a voltage value corresponding to the second characteristic point. The first and the second characteristic curves, and the characteristic boundary line define an operation range. The battery is charged/discharged within the operation range. | 05-31-2012 |
20120156586 | FUEL DISTRIBUTION STRUCTURE AND FUEL CELL HAVING THE SAME - A fuel distribution structure including a first material layer, a second material layer, a flow channel layer and a filler is provided. The first material layer has a fuel inlet, the second material layer has a plurality of fuel outlets, the flow channel layer has a patterned flow channel, wherein the fuel inlet and the fuel outlets are covered by a distribution range of the patterned flow channel, and the filler is disposed in the patterned flow channel. In addition, a fuel cell having the above-mentioned fuel distribution structure is also provided. | 06-21-2012 |
20150243939 | CAP ASSEMBLY FOR BATTERY - A cap assembly for a battery includes a roll combination member, a terminal combination member, an electrode terminal, a strength reinforcing block, a cap, and a pad assembly. The roll combination member includes at least one opening, so that terminal disposed portions of 2k rolls are capable of passing through the opening and k is an integer greater than 1, wherein one terminal disposed portion is formed by bending portions of central members of two adjacent rolls. The terminal combination member, the electrode terminal, the strength reinforcing block, the cap, and the pad assembly are sequentially combined on the roll combination member, wherein the electrode terminal includes an electrically conductive portion and a thermally conductive portion which surrounds the electrically conductive portion. The cap assembly is electrically connected to the bending portions at the same side of the 2k rolls. | 08-27-2015 |
Patent application number | Description | Published |
20110206052 | DATA TRANSFER SYSTEM ENABLING ACCESS TO MULTIPLE SUBNETS AND METHOD THEREOF - A data transfer system enabling access to multiple subnets and method thereof is disclosed. The data transfer method includes the following steps: executing a virtual private network (VPN) client installed on an electronic system; connecting the VPN client to a VPN router; the VPN client assigning a virtual IP address to a virtual interface; and the VPN client accessing a subnet corresponding to the virtual IP address through the virtual IP address. | 08-25-2011 |
20120020215 | WIRELESS NETWORK SYSTEM AND WIRELESS ACCESS POINT DEVICE THEREOF - A wireless network system and a wireless access point (AP) device thereof are provided. The wireless network system includes at least a wireless AP device and a plurality of wireless terminal devices. Each wireless AP device maintains a load list including load states of all wireless AP devices in the same area, and ranks load states of all wireless AP devices in the load list at least according to central processing unit utilization rates of the wireless AP devices. When a wireless terminal device transmits a connection request to one wireless AP device, the wireless AP determines whether it being in a low load state, and decides, depending upon whether it being in the low load state, to accept the connection request or to notify one or a plurality of wireless AP devices being in the low load states in the same area to accept the connection request. | 01-26-2012 |
20120020339 | WIRELESS NETWORK SYSTEM AND WIRELESS ACCESS POINT DEVICE AND WIRELESS TERMINAL DEVICE THEREOF - A wireless network system and a wireless access point (AP) device and a wireless terminal device thereof are provided. The wireless network system includes at least a wireless AP device and at least a wireless terminal device. Each wireless AP device broadcasts a beacon including a load state content of the wireless AP device. Each wireless terminal device receives beacons of all wireless AP devices, and ranks load states of all wireless AP devices in a load list according to at least CPU utilization rates in the load state contents of all wireless AP devices respectively. When a wireless terminal device intends to establish a connection with one of the wireless AP devices, the wireless terminal devices searches through the load list to select a wireless AP device being in a low load state, and transmits a connection request message to the selected wireless AP device. | 01-26-2012 |
20120023325 | VIRTUAL PRIVATE NETWORK SYSTEM AND NETWORK DEVICE THEREOF - A virtual private network (VPN) system and a network device thereof are provided. The VPN system includes a first network device, a second network device, and an authentication server. The first network device provides an encrypted connection setup request message containing an authentication information to the second network device. The second network device receives the encrypted connection setup request message and forwards the authentication information to the authentication server to perform a first authentication process, so as to determine whether the first network device is authorized. If the first network device is authorized, the first network device and the second network device directly exchange a set of VPN arguments and perform a second authentication process through the exchange of the VPN arguments, so as to establish an IPSec VPN connection between the first network device and the second network device. | 01-26-2012 |
20120092186 | WIRELESS COMMUNICATION DEVICE - A wireless communication device adapted for transmitting and receiving information in a wireless access in vehicular environment (WAVE) is proposed. The wireless communication device includes a WAVE module. The WAVE module broadcasts a WAVE announcement frame as a beacon, where the beacon includes a WAVE service information element (WSIE), and the WSIE includes at least record information such as a vehicle number of a vehicle, in which the wireless communication device is located. Another wireless communication device is proposed, which exchanges respective record information with the neighboring vehicle(s) via a connection established between the wireless communication device and the neighboring vehicle(s) after at least a WAVE announcement frame of the neighboring vehicle(s) is received. | 04-19-2012 |
20120122501 | WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREOF - A wireless communication system and a wireless communication device thereof are proposed. The system is adapted for synchronizing wireless setting of at least a wireless communication device in the system. The at least a wireless communication device synchronizes a first wireless setting thereof or synchronizes a second wireless setting of another wireless communication device in the system by just wireless network signal. Moreover, the at least a wireless communication device determines whether the first wireless setting thereof is the latest by checking a sequence number in the wireless network signal. | 05-17-2012 |
Patent application number | Description | Published |
20130148518 | PACKET RECEIVER AND PACKET PROCESSING METHOD THEREOF - A packet processing method applied in a packet receiver is provided. An approximate bit rate is first determined according to time stamps of two different packets. The approximate bit rate is corrected according to a time stamp of another packet to generate a fine-tuned bit rate. According to the fine-tuned bit rate, one or more subsequent packets are read out from a buffer. The time stamp of a subsequent packet is provided according to the approximate bit rate. | 06-13-2013 |
20140177758 | TIMING RECOVERY APPARATUS AND METHOD - A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal. | 06-26-2014 |
20140179254 | CARRIER FREQUENCY OFFSET COMPENSATION APPARATUS AND ASSOCIATED METHOD - A carrier frequency offset compensation method for a communication system is provided. The method includes: mixing, filtering and interpolating an input signal according to a mixing parameter, a first filtering parameter and a first interpolation parameter, respectively, to generate a processed result; calculating a carrier frequency offset estimation value of the input signal according to the processed result; adjusting the mixing parameter according to the carrier frequency offset estimation value; and mixing, filtering and interpolating the input signal according to the adjusted mixing parameter, a second filtering parameter and a second interpolation parameter, respectively. The first interpolation parameter is associated with a cut-off frequency corresponding to the first filtering parameter. | 06-26-2014 |
20140355659 | RECEIVING APPARATUS AND METHOD FOR ACCELERATING EQUALIZATION CONVERGENCE - A receiving apparatus applied to a receiving end of a communication device having an equalizer is provided. The receiving apparatus includes a filter and a channel estimator. The filter filters a received signal to reduce a multipath effect of the received signal and outputs a filtered signal. The channel estimator performs channel estimation on the received signal to generate an estimation result. The estimation result is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer. | 12-04-2014 |
Patent application number | Description | Published |
20110258495 | METHODS OF CALCULATING COMPENSATION VOLTAGE AND ADJUSTING THRESHOLD VOLTAGE AND MEMORY APPARATUS AND CONTROLLER - Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage. | 10-20-2011 |
20110258496 | DATA READING METHOD, MEMORY STORAGE APPARATUS AND MEMORY CONTROLLER THEREOF - A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read. | 10-20-2011 |
20110317488 | DATA READING METHOD AND CONTROL CIRCUIT AND MEMORY CONTROLLER USING THE SAME - A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information. | 12-29-2011 |
20120072805 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD THEREOF FOR GENERATING LOG LIKELIHOOD RATIO - A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data. | 03-22-2012 |
20120311402 | DATA READING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE - A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information. | 12-06-2012 |
20140047300 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF - A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module. | 02-13-2014 |
20140293696 | DATA READING METHOD, AND CONTROL CIRCUIT, MEMORY MODULE AND MEMORY STORAGE APPARATUS AND MEMORY MODULE USING THE SAME - A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing. | 10-02-2014 |
20150067446 | DECODING METHOD, MEMORY STORAGE DEVICE AND REWRITABLE NON-VOLATILE MEMORY MODULE - A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased. | 03-05-2015 |
20150095741 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved. | 04-02-2015 |
20150186212 | DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased. | 07-02-2015 |
20150293811 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved. | 10-15-2015 |
20150293813 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit. | 10-15-2015 |
20150331742 | DATA MANAGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command. | 11-19-2015 |
20160098316 | ERROR PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably. | 04-07-2016 |
Patent application number | Description | Published |
20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
20100002344 | HIGH VOLTAGE TOLERANCE CIRCUIT - A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad. | 01-07-2010 |
20100006924 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region. | 01-14-2010 |
20100073985 | METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage. | 03-25-2010 |
20100265755 | ONE TIME PROGRAMMABLE READ ONLY MEMORY AND PROGRAMMING METHOD THEREOF - A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction. | 10-21-2010 |
20140361358 | NONVOLATILE MEMORY STRUCTURE - A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor. | 12-11-2014 |