Patent application number | Description | Published |
20100218621 | SAMPLE PROCESSING METHODS - A method of processing a sample may include introducing a sample into a vessel, the vessel having proximal and distal ends, the sample being introduced into the proximal end of the vessel; incubating the sample in the vessel with a substance capable of specific binding to a preselected component of the sample; propelling components of the incubated sample, other than the preselected component, toward the proximal end of the vessel by clamping the vessel distal to the incubated sample and compressing the vessel where the incubated sample is contained; propelling the preselected component toward a distal segment of the vessel by clamping the vessel proximal to the preselected component and compressing the vessel where the preselected component is contained; and mixing the preselected component with a reagent in the distal segment of the vessel. | 09-02-2010 |
20100323919 | SAMPLE MULTIPROCESSING - A sample processing vessel may include a branch segment and at least two tracks. The at least two tracks may be fluidly isolated from one another by a permanent seal. The tracks may be segmented by breakable seals. The branch segment may be temporarily isolated from the tracks by breakable seal(s) and put in fluid communication with the tracks once those seal(s) are broken, such that fluid received by the branch segment is divided into portions that pass into both tracks. | 12-23-2010 |
20110143968 | SAMPLE VESSELS - A sample vessel may include a segmented tubule and an interface receiving the tubule. The segmented tubule may include an opening for receiving a sample material and at least one compressible section, the at least one compressible section having a wall constructed at least partially from a material having sufficient flexibility to permit compression of opposed sections of the wall into contact with one another, and at least two segments of the tubule being fluidically isolated from one another by a bonding of a fluid-tight seal between opposed sections of the tubule wall, wherein said fluid-tight seal irreversibly opens upon application of fluid pressure greater than a threshold value to permit selective fluid communication between the opposed sections. The interface may facilitate delivery of a sample material to the tubule through the opening. | 06-16-2011 |
Patent application number | Description | Published |
20080246773 | INDEXES OF GRAPHICS PROCESSING OBJECTS IN GRAPHICS PROCESSING UNIT COMMANDS - This disclosure describes techniques of loading batch commands into a graphics processing unit (GPU). As described herein, a GPU driver for the GPU identifies one or more graphics processing objects to be used by the GPU in order to render a batch of graphics primitives. The GPU driver may insert indexes associated with the identified graphics processing objects into a batch command. The GPU driver may then issue the batch command to the GPU. The GPU may use the indexes in the batch command to retrieve the graphics processing objects from memory. After retrieving the graphics processing objects from memory, the GPU may use the graphics processing objects to render the batch of graphics primitives. | 10-09-2008 |
20080252652 | PROGRAMMABLE GRAPHICS PROCESSING ELEMENT - In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object. | 10-16-2008 |
20080273031 | Page based rendering in 3D graphics system - A method of rendering 3D graphics image includes the steps of: storing the primitives information into the primitive bank and parameter bank whose entries are made up the primitive IDs; converting the primitives into the pages whose coordinates are made up the page IDs; matching incoming page IDs of the incoming primitive with the page IDs stored in the page RAM in such a manner that when the incoming page ID of the incoming primitive matches with the sorted page ID stored in the page RAM, the incoming primitive are added to the corresponding page node in the page RAM under the corresponding page ID; flushing the page RAM when the free page nodes of the page RAM less than a predetermined amount or when the primitive's counter of the page node reaches another predetermined number; and rendering the primitives stored in the page memory into pixels. | 11-06-2008 |
20090033672 | SCHEME FOR VARYING PACKING AND LINKING IN GRAPHICS SYSTEMS - A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium. | 02-05-2009 |
20090085919 | SYSTEM AND METHOD OF MAPPING SHADER VARIABLES INTO PHYSICAL REGISTERS - The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types. | 04-02-2009 |
20090113402 | SERVER-BASED CODE COMPILATION - A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client. | 04-30-2009 |
20100302246 | GRAPHICS PROCESSING UNIT WITH DEFERRED VERTEX SHADING - Techniques are described for processing graphics images with a graphics processing unit (GPU) using deferred vertex shading. An example method includes the following: generating, within a processing pipeline of a graphics processing unit (GPU), vertex coordinates for vertices of each primitive within an image geometry, wherein the vertex coordinates comprise a location and a perspective parameter for each one of the vertices, and wherein the image geometry represents a graphics image; identifying, within the processing pipeline of the GPU, visible primitives within the image geometry based upon the vertex coordinates; and, responsive to identifying the visible primitives, generating, within the processing pipeline of the GPU, vertex attributes only for the vertices of the visible primitives in order to determine surface properties of the graphics image. | 12-02-2010 |
20120256921 | 3-D CLIPPING IN A GRAPHICS PROCESSING UNIT - A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping. | 10-11-2012 |
20120268484 | METHOD AND DEVICE FOR PERFORMING USER-DEFINED CLIPPING IN OBJECT SPACE - A method and device for performing and processing user-defined clipping in object space to reduce the number of computations needed for the clipping operation. The method and device also combine the modelview transformation of the vertex coordinates with projection transform. The user-defined clipping in object space provides a higher performance and less power consumption by avoiding generation of eye coordinates if there is no lighting. The device includes a driver for the user-defined clipping in the object space to perform dual mode user-defined clipping in object space when a lighting function is disabled and in eye space when the lighting function is enabled. | 10-25-2012 |
20130328889 | PADDING FOR MULTI-CHANNEL MEMORY - Techniques described in the disclosure are generally related to reserving padding bytes in system memory when storing data in the system memory. The reserving of padding bytes may allow a memory interface to efficiently utilize the channels to the system memory when storing or subsequently retrieving the data. | 12-12-2013 |