Surico
Francesco Surico, Milano IT
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20130065988 | SUPERPLASTICIZERS FOR CONCRETE AND CEMENT MATERIALS AND PROCESS FOR PRODUCING THE SAME - Superplasticizer for concrete and other cement mixtures, which is intrinsically low-foaming, promotes the early mechanical strength development and retains the workability of fresh concrete for longer time, obtainable by reacting acid, not neutralized, polycarboxylic polymers with monofunctional polyethers and difunctional polyethers in the absence of strong acidic catalysts. | 03-14-2013 |
20140296370 | METHOD FOR PRODUCING AGGREGATES FROM CEMENT COMPOSITIONS - A method for producing aggregates from fresh cement compositions, included concrete and residual concrete is disclosed, comprising the addition of a) flash setting accelerators and b) super-absorbent polymers to fresh unset cement compositions and blending this mixture until granular materials are formed. | 10-02-2014 |
Stefano Surico, Milano IT
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20080246504 | APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE - A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers. | 10-09-2008 |
20080250191 | FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY - A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface. | 10-09-2008 |
20080310232 | ERASE VERIFY FOR MEMORY DEVICES - Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation. | 12-18-2008 |
20090290424 | METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching. | 11-26-2009 |
20120106250 | METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching. | 05-03-2012 |
Stefano Surico, Bussero (mi) IT
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20130016564 | ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICESAANM Ferragina; VincenzoAACI San Genesio ed Uniti (PV)AACO ITAAGP Ferragina; Vincenzo San Genesio ed Uniti (PV) ITAANM Surico; StefanoAACI Bussero (MI)AACO ITAAGP Surico; Stefano Bussero (MI) ITAANM Moioli; GiuseppeAACI Albino (BG)AACO ITAAGP Moioli; Giuseppe Albino (BG) ITAANM Bartoli; SimoneAACI Mandello del Lario (LC)AACO ITAAGP Bartoli; Simone Mandello del Lario (LC) IT - Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage. | 01-17-2013 |
20140293707 | Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices - Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage. | 10-02-2014 |
20140372666 | SEMICONDUCTOR DEVICE WITH CONFIGURABLE SUPPORT FOR MULTIPLE COMMAND SPECIFICATIONS, AND METHOD REGARDING THE SAME - A device includes a NAND flash memory, and a generic command interface configured to interpret both an Open NAND Flash Interface specification and a first NAND flash specification to perform an associated one of command operations on the NAND flash memory, the Open NAND Flash Interface specification and the first NAND flash specification being different from each other. | 12-18-2014 |
Stefano Surico, Bussero IT
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20130033947 | CLOCK GENERATOR - Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal. | 02-07-2013 |
20140173173 | METHOD, DEVICE, AND SYSTEM INCLUDING CONFIGURABLE BIT-PER-CELL CAPABILITY - A method includes providing a partition command to a device that includes a memory array including a plurality of memory cells. In response to the providing of the partition command, the memory cells of the memory array are partitioned to select a portion of the memory array. In response to the providing of the partition command, one of bit numbers that are to be stored in one memory cell is selected, so that each of the memory cells included in the selected portion stores data with the selected one of the bit numbers. | 06-19-2014 |
Stefano Surico, Agrate Brianza (mb) IT
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20130135007 | LOGIC CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANAGING AN OPERATION IN THE SEMICONDUCTOR MEMORY DEVICE - A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid. | 05-30-2013 |