Patent application number | Description | Published |
20090123534 | Pharmaceutical composition based on micronized progesterone, preparation method and uses thereof - The present invention relates to a pharmaceutical composition comprising micronized progesterone, soya bean lecithin, and at least one oil selected from the group consisting of sunflower oil, olive oil, sesame seed oil, colza oil, almond oil, to the method for the preparation thereof and to the uses thereof for treating a physiological condition linked to insufficiency of progesterone secretion. | 05-14-2009 |
20110135719 | PHARMACEUTICAL COMPOSITION BASED ON MICRONIZED PROGESTERONE, PREPARATION METHOD AND USES THEREOF - The present invention relates to a pharmaceutical composition comprising micronized progesterone, soya bean lecithin, and at least one oil selected from the group consisting of sunflower oil, olive oil, sesame see oil, colza oil, almond oil, to the method for the preparation thereof and to the uses thereof for treating a physiological condition linked to insufficiency of progesterone secretion. | 06-09-2011 |
Patent application number | Description | Published |
20100215806 | HEAT-RESISTANT COMPOSITION FOR ANIMALS COMPRISING AN ENZYMATIC MIXTURE - The invention relates to a heat-resistant composition for animals in the form of a granular powder, comprising: a) a liquid mixture of at least two enzymes; b) a medium selected from the group comprising wheat flour, starch, gypsum, maltodextrin, and corn cobs; and c) a coating agent selected from the group comprising cellulose and the derivatives thereof, chitin, carrageenan, sodium alginate, vegetable gums, gums obtained using a fermentation process, and starches and derivatives. | 08-26-2010 |
20140113025 | HEAT-RESISTANT COMPOSITION FOR ANIMALS, COMPRISING AN ENZYMATIC MIXTURE - The invention relates to a heat-resistant composition for animals in the form of a granular powder, comprising: a) a liquid mixture of at least two enzymes; b) a medium selected from the group comprising wheat flour, starch, gypsum, maltodextrin, and corn cobs; and c) a coating agent selected from the group comprising cellulose and the derivatives thereof, chitin, carrageenan, sodium alginate, vegetable gums, gums obtained using a fermentation process, and starches and derivatives. | 04-24-2014 |
Patent application number | Description | Published |
20150049406 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT ARRANGEMENT, ELECTRONIC CIRCUIT AND ESD PROTECTION METHOD - An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold. | 02-19-2015 |
20150061728 | ELECTRONIC DEVICE AND METHOD FOR MAINTAINING FUNCTIONALITY OF AN INTEGRATED CIRCUIT DURING ELECTRICAL AGGRESSIONS - An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed. | 03-05-2015 |
20150076556 | INTEGRATED CIRCUIT DEVICE AND A METHOD FOR PROVIDING ESD PROTECTION - An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node. | 03-19-2015 |
20150098160 | PROTECTION CIRCUIT AND A GATE DRIVING CIRCUITRY - A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref. | 04-09-2015 |
20150129928 | PACKAGED SEMICONDUCTOR DEVICE, A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component. | 05-14-2015 |
20150221629 | SEMICONDUCTOR DEVICE AND AN INTEGRATED CIRCUIT COMPRISING AN ESD PROTECTION DEVICE, ESD PROTECTION DEVICES AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad. | 08-06-2015 |
20150221633 | SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage. | 08-06-2015 |
20150276815 | HIGH BANDWIDTH CURRENT SENSOR AND METHOD THEREFOR - A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device. | 10-01-2015 |
20150276847 | METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR DEVICE AGAINST ELECTROSTATIC DISCHARGE - A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time. | 10-01-2015 |
20150311193 | A SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region. | 10-29-2015 |
20150369845 | INTEGRATED CIRCUIT WITH INTEGRATED CURRENT SENSOR - An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. The electronic circuit comprises a first electric contact, a second electric contact, and a coupling which couples the electric strips electrically to each other. The coupling includes a circuit via which extends through at least two of the layers. The die further includes an integrated current sensor having a coil arrangement for sensing a current flowing through a part of the electronic circuit. The coil arrangement is magnetically coupled to the circuit via over at least a part of a length of the circuit via to sensing a magnetic flux through the circuit via. A measurement unit can measure a parameter of the coil arrangement representative of a current flowing through the circuit via. | 12-24-2015 |
Patent application number | Description | Published |
20080246345 | Semiconductor Switch Arrangement and an Electronic Device - A semiconductor switch arrangement ( | 10-09-2008 |
20090057833 | SEMICONDUCTOR DEVICE STRUCTURE AND INTEGRATED CIRCUIT THEREFOR - A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements. | 03-05-2009 |
20090116157 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND METHOD THEREFOR - An electrostatic discharge protection apparatus comprises a stack arrangement having a first electrostatic discharge protection element and a second electrostatic discharge protection element. The stack arrangement is arranged to provide a bias potential between the first and second electrostatic discharge protection elements. In one embodiment, the bias potential can be achieved by a clamp arrangement coupled across the stack arrangement. | 05-07-2009 |
20100127305 | ESD PROTECTION DEVICE AND METHOD OF FORMING AN ESD PROTECTION DEVICE - An ESD protection device, which is arranged to be active at a triggering voltage (Vt | 05-27-2010 |
20100128402 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR - An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector, coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s). | 05-27-2010 |
20110058293 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, EQUIPMENT AND METHOD - An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off. | 03-10-2011 |
20110084339 | SEMICONDUCTOR DEVICE AND METHOD OF ELECTROSTATIC DISCHARGE PROTECTION THEREFOR - A semiconductor device comprises at least one switching element. The at least one switching element comprises a first channel terminal, a second channel terminal and a switching terminal, the switching element being arranged such that an impedance of the switching element between the first and second channel terminals is dependant upon a voltage across the switching terminal and the first channel terminal. The semiconductor device further comprises a resistance element operably coupled between the first channel terminal of the at least one switching element and a reference node, and a clamping structure operably coupled between the switching terminal of the switching element and the reference node. The resistance element and the clamping structure are arranged such that, when current flowing through the at least one switching element, between the first and second channel terminals, exceeds a threshold current value, a voltage drop across the resistance element exceeds a difference between (i) a clamping voltage of the clamping structure and (ii) a switching voltage threshold of the at least one switching element, causing the impedance between the first and second channel terminals of the at least one switching component to increase. | 04-14-2011 |
20110175592 | BUS DRIVER FOR AVOIDING AN OVERVOLTAGE - An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage. | 07-21-2011 |
20110180876 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device. When a negative current is encountered at the first channel terminal, the negative current causes both a voltage drop across the switching terminal and the first channel terminal and a voltage drop across the second channel terminal and the switching terminal. | 07-28-2011 |
20130056792 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR - An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit. The first and second switching devices are arranged so as to provide, when in use, a bidirectional snapback characteristic and a snapback voltage associated therewith. | 03-07-2013 |