Patent application number | Description | Published |
20130138535 | NETWORK SECURE PAY-AS-YOU-GO SYSTEM - The present technical scheme relates to a network secure pay-as-you-go system, especially to a network secure pay-as-you-go system capable of confirming the identities of buyers and sellers in advance. The system includes a transaction platform unit, at least one buyer processing end and at least one seller processing end. The transaction platform unit provides at least one vending message distribution, and the transaction platform unit has at least one entity account. The buyer processing end can connect with the transaction platform unit through the Internet, and the buyer processing end has at least one buyer bank account of an entity financial institution. The seller processing end connects with the transaction platform unit through the Internet, and the seller processing end has at least one seller bank account of the entity financial institution. The identities of buyers and sellers are confirmed in advance when the entity financial institution opens an account, and buyers prepay money to the network transaction platform when the buyers purchase merchandise, and a network transaction construction end pays money to the sellers after completing the transaction. The system reduces the phenomenon of the transaction on behalf of others such that the security in transaction is improved. | 05-30-2013 |
20140040132 | MOBILE DEVICE PAY METHOD - The present invention relates to a micropayment transaction technology, more particularly, the present invention relates to a mobile device payment method, which is able to control consumption and enhance transaction security for buyer. The present invention is able to process payment by letting the buyer register personal account number in a transaction platform in advance via a mobile device and generating a numbered account after verification for later prepay consumption. Thus, the numbered account and the mobile device are applied for user's personal identification. Thus the user is able to control consumption efficiently, and the prepayment or the consumption both need identification to prevent credit card from been stolen or leaked out and fraud financial transaction, and the transaction security is highly increased. | 02-06-2014 |
20140325219 | SECRET KEY MANAGEMENT METHOD FOR MULTI-NETWORK PLATFORM - In a secret key management method for multi-network platform, when the user logs in any network platform via arbitrary web-browser, the network platform links to the private cloud by Hypertext Transfer Protocol Daemon (HTTPD), and the private cloud shows a timeliness operational parameter on the web-browser for the user inputting personal parameters, and when the user inputs personal parameters within the predetermined time period, the private cloud then generates a pass key; the pass key generated by the private cloud is adapted to cooperate with the pass lock which is generated by the private cloud when the user registered to identify the user, and the identification result is transmitted to the network platform, and the network platform is configured to use the pass lock and pass key to identify the user. | 10-30-2014 |
20150209617 | FITNESS EQUIPMENT COMBINING WITH A CLOUD SERVICE SYSTEM - A fitness equipment combining with a cloud service system includes a control device, an exercise unit, a transmission module and a display module. The cloud service system includes a transceiver server, a computing server and a storage server. A control signal and a power signal which are generated respectively by the control device and the exercise unit according to manipulation and operation of a user are transmitted via the transmission module to the transceiver server. The computing server establishes an exercise model according to the control signal and power signal and combines the exercise model with an information model stored in the storage server to generate a display signal. The display signal is inputted to the display module to generate an interactive image. Accordingly, the cloud service system can be simultaneously connected with multiple fitness equipment for competition, so as to create much fun for exercise. | 07-30-2015 |
Patent application number | Description | Published |
20100207671 | FREQUENCY DIVIDING CIRCUIT - A frequency dividing circuit performs a frequency dividing operation on N input clock signals to obtain N output clock signals, wherein N is a natural number greater than 1. The frequency dividing circuit includes a frequency divider and a flip-flop. The frequency divider samples an initial signal according to a first input clock signal of the N input clock signals to accordingly generate a first output clock signal of the N output clock signals. The initial signal corresponds with an inverse signal of the first output clock signal. The flip-flop samples the first output clock signal to accordingly generate a second output clock signal of the N output clock signals according to a second input clock signal of the N input clock signals. | 08-19-2010 |
20100215130 | Method and Related Device for Detecting Signals in a TMDS Transmission System - A method for detecting signals in a TMDS transmission system is disclosed. A channel of the TMDS system is established between a receiver and a transmitter. The method includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference. | 08-26-2010 |
20100259106 | SWITCHING CONTROL METHOD CAPABLE OF CONTINUOUSLY PROVIDING POWER AND RELATED APPARATUS AND POWER SUPPLY SYSTEM - A switching control method capable of continuously providing power is utilized for a power supply system having a first power supply unit and a second power supply unit. The switching control method includes generating a first input signal and a second input signal; performing a logical operation process on the first input signal and the second input signal to generate a first control signal; delaying the second input signal for a delay time to generate a second control signal; controlling a coupling relationship between the first power supply unit and a load according to the first control signal; and controlling a coupling relationship between the second power supply unit and the load according to the second control signal. | 10-14-2010 |
20110012689 | Impedance Adjustment Circuit for Adjusting Terminal Resistance and Related Method - An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal. | 01-20-2011 |
20110032977 | Dual-Port Input Equalizer - A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit. | 02-10-2011 |
20120194237 | DELAY LOCK LOOP AND METHOD FOR GENERATING CLOCK SIGNAL - A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided. | 08-02-2012 |
20140064340 | DIFFERENTIAL SIGNAL TRANSMISSION CIRCUIT - A differential signal transmission circuit including a pattern generator, a low voltage differential signal (LVDS) transmitter, a transition minimized differential signal (TMDS) receiver, and a comparator is provided. The pattern generator generates a plurality of test data. The LVDS transmitter is coupled to the pattern generator to receive the test data, and generates a test output signal according to the test data. The TMDS receiver receives a test input signal to output a plurality of decoded data. The comparator is coupled to the TMDS receiver to receive the decoded data and the pattern generator to receive the test data. The comparator compares the decoded data with the test data to output a test result of the TMDS receiver. | 03-06-2014 |
20160072478 | INTEGRATED CIRCUIT - An integrated circuit is provided. The integrated circuit includes a pad, a core circuit, an impedance matching component, a first switch and a second switch. The pad is configured to transmit a communication signal. A communication terminal of the core circuit is coupled to the pad, and a power terminal of the core circuit is coupled to a system voltage rail. A first terminal of the impedance matching component is coupled to the pad. A first terminal of the first switch is coupled to the system voltage rail, and a second terminal of the first switch is coupled to a second terminal of the impedance matching component. A first terminal of the second switch is coupled to a control terminal of the first switch, and a second terminal of the second switch is coupled to the second terminal of the impedance matching component. | 03-10-2016 |
20160072593 | TRANSCEIVER AND OPERATION METHOD THEREOF - A transceiver and an operation method thereof are provided. The transceiver includes a transmitter and a receiver. The transmitter is configured to receive an output reference signal to provide an output signal to a signal channel. The receiver is coupled to the signal channel to receive a receiving reference signal to provide a receiving signal. The receiver includes a comparator unit and a signal adjusting unit. The comparator unit is configured to compare a first signal and a second signal to obtain the receiving signal. The signal adjusting unit is coupled between the output reference signal, the receiving reference signal and the comparator unit to adjust a voltage level of at least one of the output reference signal and the receiving reference signal to obtain the first signal and the second signal. | 03-10-2016 |
Patent application number | Description | Published |
20130045374 | NANO-LAMINATED FILM WITH TRANSPARENT CONDUCTIVE PROPERTY AND WATER-VAPOR RESISTANCE FUNCTION AND METHOD THEREOF - The present invention discloses a nano-laminated film with transparent conductive property and water-vapor resistance function and method thereof. The nano-laminated film comprises a plurality of first metal oxide layers and a plurality of second metal oxide layers. Wherein, the first metal layers and the second metal layers are made of different materials, and there is a spinel phase formed between the first metal layers and the second metal layers. | 02-21-2013 |
20130256262 | In Situ Manufacturing Process Monitoring System of Extreme Smooth Thin Film and Method Thereof - An in situ manufacturing process monitoring system of extreme smooth thin film and method thereof, comprising a coating device for coating a thin film on at least one substrate during a coating process, an ion figuring device for processing a surface polishing process on the thin film, a control device electrically coupled to the coating device and the ion figuring device respectively for controlling the coating device and the ion figuring device processing the coating process and surface polishing process by adjusting at least one device parameter of the coating device and the ion figuring device, and an in situ monitoring device electrically coupled to the control device for in situ monitoring at least one optical parameter of the thin film. | 10-03-2013 |
20160025871 | MAGNETRON SPUTTERING GUN ASSEMBLY - A magnetron sputtering gun device used in vacuum for sputtering to form a thin film, which comprises a magnet copper seat, a magnetic element, a conductive element, a sputtering target, a target fixation assembly, a cylinder-shape protection mask, and a sputtering inclination assembly. By enhancing the magnet copper seat, the magnetron sputtering gun device is equipped with capability of increased film coating speed and increased compound ability between the thin film and the reaction gas. A ferromagnetic material may be coated. The magnet copper seat may be designed so that the sputtering target and strong magnets therewithin may be conveniently detached. In this structure, a cooling water tubing and the strong magnets are separated, lengthening a lifetime of the strong magnets and protecting the strong magnets from demagnetization. The sputtering inclination assembly may further increase a uniformity of the thin film thickness. | 01-28-2016 |
Patent application number | Description | Published |
20140362649 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell groups, a data line unit, a buffer unit and a bias voltage unit. The data line unit is coupled to the memory cell groups for transmitting to-be-read data and to-be-written data. The buffer unit includes a plurality of tri-state buffers coupled to the data unit. The bias voltage unit is coupled to the data unit to supply a preset bias voltage thereto. The tri-state buffers segment the data line unit into smaller units, thereby reducing parasitic capacitance of the data line unit, and consequently the power consumption of the semiconductor memory device. | 12-11-2014 |
20150016197 | SEMICONDUCTOR MEMORY DEVICE THAT DOES NOT REQUIRE A SENSE AMPLIFIER - A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an output terminal coupled to a data line unit. The tri-state buffer is operable to switch between a conducting state and a non-conducting state. The bias voltage unit controls supply of a preset bias voltage to the input terminal of the tri-state buffer. By using the tri-state buffer, the parasitic capacitance attributed to the memory cell can be reduced, such that no sense amplifier is required to ensure proper operation, thereby reducing power consumption. | 01-15-2015 |
20150279435 | LOW POWER MEMORY DEVICE - A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured. | 10-01-2015 |
20160034220 | LOW POWER CONSUMPTION MEMORY DEVICE - A memory device includes a plurality of memory modules and a plurality of control lines. Each memory module includes a plurality of memory units. Each memory unit includes: a plurality of memory cell groups, each of which includes at least one memory cell; a plurality of first bit lines, each of which is coupled to the at least one memory cell of a respective memory cell group; a second bit line; and a plurality of controllable circuits, each of which has an input terminal coupled to a respective first bit line, an output terminal coupled to the second bit line, and a control terminal. Each control line is coupled to the control terminal of a corresponding controllable circuit of each of at least one memory unit of each memory module. The memory device consumes relatively small power. | 02-04-2016 |
20160111145 | 6T SRAM CELL - A 6T SRAM cell includes a write inverter which includes a write pull-up transistor and a write pull-down transistor, a read inverter which includes a read pull-up transistor and a read pull-down transistor, a write access transistor, and a read access transistor. To-be-written data is written into the 6T SRAM cell via the write access transistor in a one-sided write operation, and to-be-read data is read via the read access transistor in a one-sided read operation. Equivalent resistance of the read pull-up transistor is smaller than that of the read access transistor, and equivalent resistance of the read pull-down transistor is smaller than that of the read access transistor. | 04-21-2016 |
Patent application number | Description | Published |
20100321340 | System and Method of Distinguishing Multiple Touch Points - The invention discloses a method of distinguishing multiple touch points applied to an optical touch system which includes a panel for indicating a first touch point and a second touch point thereon and a camera unit for capturing an image relative to the first touch point and the second touch point. The image has a first dark area and a second dark area corresponding to the first touch point and the second touch point respectively. In the method, if it is observed that the first dark area and the second dark area merge into a first single dark area and a second single dark area at current time and previous time respectively, the respective positions of the first dark area and the second dark area are determined based on the respective union dark area widths of the first single dark area and the second single dark area, and the respective coordinates of the first touch point and the second touch point are determined according to the respective positions of the first dark area and the second dark area. | 12-23-2010 |
20110102376 | Image-Based Coordinate Input Apparatus and Method Utilizing Buffered Imates - The invention provides an image-based coordinate input apparatus and method for detecting positions of N objects on a coordinate input region at a detecting interval where N equals to 1 or 2. According to the invention, starting at the start of the detecting interval, successive first images at a first view and successive second images at a second view relative to the N objects and a background of the perimeter of the coordinate input region are captured and buffered. The apparatus and method according to the invention judges the number of the N objects and calculates the positions of the N objects on the coordinate input region at the detecting interval in accordance with the buffered successive first images and the buffered successive second images. | 05-05-2011 |
20110119579 | METHOD OF TURNING OVER THREE-DIMENSIONAL GRAPHIC OBJECT BY USE OF TOUCH SENSITIVE INPUT DEVICE - The invention provides a method of turning over a three-dimensional graphic object by use of a touch sensitive input device. In particular, the method according to the invention provides a user with intuitive operation on a touch sensitive surface of the touch sensitive input device to turn over whole or a portion (e.g., a page sub-object) of the three-dimensional graphic object. | 05-19-2011 |
Patent application number | Description | Published |
20130092484 | BRAKING DEVICE - A braking device includes a base, a braking component, and a driving component including a reset member. The braking component has a clamping block. The driving component includes a movable member, a chamber therein and a first butting portion. The movable member passes through the driving member. One end of the movable member has a piston accommodated in the chamber, and the other end of the movable member has a second butting portion. The reset member is disposed in the chamber. The piston butts the reset member under an external force, and the first butting portion and the second butting portion are kept away from each other, and when the external force vanishes, the reset member butts the piston, and the first butting portion and the second butting portion are kept close to each other so as to achieve a braking effect. | 04-18-2013 |
20130145875 | BACKLASH ELIMINATING DEVICE FOR HELICAL GEARS - A backlash eliminating device for helical gears is provided for a gear transmission system which includes a transmission shaft, two helical gears and a match gear. A sleeve mounted on the transmission shaft has an outer wall, an inner wall and at least two sections of spiral grooves penetrating through the outer wall and the inner wall. The sleeve includes a transmission part and two extremity parts. The transmission part is disposed between the spiral grooves, and is fixedly connected to the transmission shaft. The extremity parts are disposed outside of the spiral grooves. The helical gears are fixedly connected to the two extremity parts. The sleeve having the spiral grooves provides a preload spring force along an axial direction of the transmission shaft, so that the two helical gears are tightly engaged with the match gear. | 06-13-2013 |
20130150205 | APPARATUS FOR ELIMINATING BACKLASH IN A PLANETARY GEAR SET - An apparatus for eliminating backlash is disclosed, which is installed between a first planet gear and a second planet gear in a planetary gear set to be used for generating a preload elastic force in a direction perpendicular to the direction of an input torque of the planetary gear set so as to eliminate a two-way backlash of the planetary gear set. | 06-13-2013 |
20140112701 | TELESCOPIC SHAFT ASSEMBLY - A telescopic shaft assembly includes a seat, a shaft body disposed movably in the seat, and a plurality of slide blocks located between the shaft body and the seat. The shaft body has a convex portion and a recessed portion opposite to each other. One end of the convex portion far away from the recessed portion has a top surface. One of the plurality of slide block is disposed on the top surface. The recessed portion has two inner side wall surfaces opposite to each other and a bottom surface located between the two inner side wall surfaces. Each of the two inner side wall surfaces forms an obtuse angle with the bottom surface. Two of the rest of the plurality of slide blocks are disposed on the two inner side wall surfaces respectively. | 04-24-2014 |
Patent application number | Description | Published |
20110013459 | METHOD OF PROGRAMMING/ERASING THE NONVOLATILE MEMORY - A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory. | 01-20-2011 |
20110235427 | Channel Hot Electron Injection Programming Method and Related Device - A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value. | 09-29-2011 |
20130083598 | Method of Programming Nonvolatile Memory - Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells. | 04-04-2013 |
Patent application number | Description | Published |
20110161690 | VOLTAGE SCALING SYSTEMS - A voltage scaling system is provided and includes a processor, a latency predictor, a controller, and a voltage supplier. The processor performs functions and includes a function unit with variable-latency. The function unit is divided into several power domains. When the processor performs the functions, the function unit generates a latency signal according to a current circuit execution speed. The latency predictor predicts performance of the processor according to the received latency signal to generate a predication signal. The controller compares a value of the predication signal with at least one reference value. The controller generates control signals according to the comparison result. The voltage supplier couples to a first voltage source providing a high voltage and a second voltage source providing a low voltage. The voltage supplier is switched to provide the high or low voltage to the power domains according to the control signals, respectively. | 06-30-2011 |
20110161719 | PROCESSING DEVICES - An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period. | 06-30-2011 |
20110314306 | PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF - A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal. | 12-22-2011 |
Patent application number | Description | Published |
20090021872 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 01-22-2009 |
20090097174 | ESD protection circuit for IC with separated power domains - An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node. | 04-16-2009 |
20090296293 | ESD PROTECTION CIRCUIT FOR DIFFERENTIAL I/O PAIR - An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events. | 12-03-2009 |
20100142107 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 06-10-2010 |
20130057237 | MULTI-PHASE SWITCHING REGULATOR AND DROOP CIRCUIT THEREFOR - The present invention discloses a multi-phase switching regulator and a droop circuit therefor. The droop circuit includes: multiple first resistors, which are coupled to corresponding phase nodes respectively to sense current through the phase nodes; a second resistor, which is coupled to the multiple first resistors; an error amplifier circuit, which has an inverting input end and a non-inverting input end, wherein the inverting input end is coupled to the second resistor and an output end of the error amplifier circuit, and the non-inverting input end is coupled to an output node; and a droop capacitor, which is coupled between the second resistor and the output node; wherein the droop circuit provides the droop signal according to a voltage drop across the second resistor or current through the second resistor. | 03-07-2013 |
Patent application number | Description | Published |
20110174714 | Drainage fitting for air-conditioner drainage device - A drainage fitting is mounted to an air-conditioner drainage device having a waste collector provided with an inlet and an outlet. The drainage fitting is composed of a drainage connector having an annular protrusion externally and defining an upper part and a lower part, between which the annular protrusion is located, the lower part being mounted inside the outlet, the annular protrusion being stopped against the waste collector; at least two guide members being fixed to the waste collector and located at two opposite sides around the outlet and each has a guide recess facing the other, and a locating member having a hollow portion, against which the upper part of the drainage connector can be stopped, and having two sides be inserted into the guide recesses to lie against the annular protrusion. Accordingly, even if the drainage connector is accidentally forced to turn, it is disabled from separation from the waste collector. | 07-21-2011 |
20120112586 | MOTOR SHIELD FOR THE DRAINAGE DEVICE OF A COOLING OR AIR-CONDITIONING SYSTEM - A motor shield covered on a motor of a drainage device over a cooling vane is disclosed to include a shield body having an arched portion and a straight portion, a guide wall disposed in the shield body and having an arched segment and a straight segment connected to the straight portion of the shield body, an airflow zone defined in the shield body in an interference relationship relative to the cooling vane and surrounded by the arched segment and straight segment of the guide wall and the arched portion and straight portion of the shield body, horizontally extending air outlets and vertically extending air outlets respectively located on the arched portion and straight portion of the shield body, and air inlets located on the periphery of the shield body. During rotation of the cooling vane, a flow of air is induced to carry heat out of the shield body through the vertically and horizontally extending air outlets efficiently. | 05-10-2012 |