Patent application number | Description | Published |
20090039897 | Systems and Methods for Scan Chain Testing Using Analog Signals - Systems and methods for utilizing analog signals for scan chain testing of a device are disclosed. At least one embodiment includes a method for utilizing an analog signal for scan chain testing of a device comprising: passing digital input signals from a test module into a signal disassembler configured to divide the digital input signals into bits corresponding to each of the digital input signals, passing the bits into a digital-to-analog converter configured to generate an analog input signal, passing the analog input signal to an analog-to-digital converter within the device under test to obtain bits corresponding to each of the digital input signals, passing the bits as inputs to scan chains within the device under test, and utilizing the bits to test the device under test by the scan chains. | 02-12-2009 |
20110299344 | A NEW LOW VOLTAGE AND LOW POWER MEMORY CELL BASED ON NANO CURRENT VOLTAGE DIVIDER CONTROLLED LOW VOLTAGE SENSE MOSFET - A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines. | 12-08-2011 |
20130208525 | SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL - A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt. | 08-15-2013 |
Patent application number | Description | Published |
20130156936 | SPUTTER GUN HAVING VARIABLE MAGNETIC STRENGTH - A sputter source is provided. The sputter source includes a shaft extending through a central region of the sputter source. A first end of the shaft is coupled to a drive and a second end of the shaft is coupled to a bottom plate. A first plate having a ramped surface is included where the first plate is stationary. A second plate having a ramped surface is provided where the second plate is disposed above the first plate such that portions of the ramped surfaces contact each other. The second plate is coupled to the shaft, wherein the second plate is operable to rotate and move axially as the shaft rotates in a first direction and wherein the second plate is operable to remain stationary as the shaft rotates in a second direction. | 06-20-2013 |
20130156937 | System and Method for Aligning Sputter Sources - Embodiments provided herein describe systems and methods for aligning sputtering sources, such as in a substrate processing tool. The substrate processing tool includes at least one sputtering source and a device. Each of sputtering sources includes a target having a central axis. The device has an axis and is detachably coupled to the at least one sputtering source. The device indicates to a user a direction in which the central axis of the target of the at least one sputtering source is oriented. | 06-20-2013 |
20140030887 | Sputtering and Aligning Multiple Layers Having Different Boundaries - Provided are methods and systems for forming discreet multilayered structures. Each structure may be deposited by in situ deposition of multiple layers at one of multiple site isolation regions provided on the same substrate for use in combinatorial processing. Alignment of different layers within each structure is provided by using two or more differently sized openings in-between one or more sputtering targets and substrate. Specifically, deposition of a first layer is performed through the first opening that defines a first deposition area. A shutter having a second smaller opening is then positioned in-between the one or more targets and substrate. Sputtering of a second layer is then performed through this second opening that defines a second deposition area. This second deposition area may be located within the first deposition area based on sizing and alignment of the openings as well as alignment of the substrate. | 01-30-2014 |
20140134849 | Combinatorial Site Isolated Plasma Assisted Deposition - An apparatus that includes a base, a sidewall extending from the base, and a lid disposed over a top of the sidewall is provided. A plasma generating source extends through a surface of the lid. A rotatable substrate support is disposed within the chamber above a surface of the base, the rotatable substrate support operable to vertically translate from the base to the lid. A first fluid inlet extends into a first surface of the sidewall and a second fluid inlet extends into a second surface of the sidewall. The plasma generating source provides a plasma activated species to a region of a surface of a substrate supported on the rotatable substrate support and a fluid delivered proximate to the region from one of the first or the second fluid inlet interacts with the plasma activated species to deposit a layer of material over the region. | 05-15-2014 |
Patent application number | Description | Published |
20080266749 | Scalable integrated circuit high density capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 10-30-2008 |
20090283858 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 11-19-2009 |
20090290283 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 11-26-2009 |
20120018843 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 01-26-2012 |