Patent application number | Description | Published |
20110131581 | Scheduling Virtual Interfaces - A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token. | 06-02-2011 |
20120290754 | Scheduling Virtual Interfaces - A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token. | 11-15-2012 |
20130198455 | CACHE MEMORY GARBAGE COLLECTOR - A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced. | 08-01-2013 |
Patent application number | Description | Published |
20100042787 | CACHE INJECTION DIRECTING TOOL - A method for directing cache injection based on actual system load may include providing a snooping-based fabric having two or more bus-coupled units. At least one of the bus-coupled units may be configured as an injection unit for directing cache injection. A snoop request may be transmitted from the injection unit to one or more destination units of the other bus-coupled unit. The snoop request may include an identification value having a function identifier. The function identifier may identify a destination function for the cache injection, where the destination function is configured to run on the destination unit. A snoop response may be transmitted from the destination unit to the injection unit in response to the snoop request. The snoop response may include a function response value indicating whether the function identifier matches a function indication of a snoop register for the destination unit. | 02-18-2010 |
20120303948 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 11-29-2012 |
20130019108 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 01-17-2013 |
20140156945 | MULTI-STAGE TRANSLATION OF PREFETCH REQUESTS - A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i−1)-th translation stage, i ε [1, . . . ,N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage. | 06-05-2014 |
Patent application number | Description | Published |
20100205379 | CACHE-LINE BASED NOTIFICATION - Embodiments of the invention provide a method, system, and computer program product for cache-line based notification. An embodiment of the method comprises injecting a cache-line including notification information into a cache of a processing unit, marking the cache-line as having the notification information, and using the notification information to notify a processing thread of the presence of the cache-line in the cache. In an embodiment, the cache-line identifies a thread affiliation. In an embodiment, a multitude of threads operate in the processing unit, and the using includes notifying a plurality of these threads of the presence of the cache-line in the cache, and analyzing the cache-line to identify this plurality of threads. The cache may include a plurality of cache-lines, each of which includes a notification, and the processing unit thread uses these notifications to form a linked list of at least some of the cache-lines. | 08-12-2010 |
20100223624 | METHOD FOR PUSHING WORK REQUEST-ASSOCIATED CONTEXTS INTO AN IO DEVICE - A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data. | 09-02-2010 |
20130007375 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |
20130007398 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |