Patent application number | Description | Published |
20110239664 | FLUID LEVEL MEASUREMENT SYSTEM AND METHOD - A transport refrigeration system for a transportable temperature controlled space includes a compressor, a condenser and an evaporator fluidly connected to one another, an engine operatively connected to the compressor, and a fuel tank assembly fluidly connected to the engine. The fuel tank assembly includes a fuel tank configured to contain the fuel, a fuel vapor and air, and an ultrasonic fluid level sensor for sensing a level of fuel, the fuel tank having a maximum fuel level. The fluid level sensor includes a transducer having a ring period. The distance from the fluid level sensor to the maximum fuel level is at least half the distance that the sound travels through the fuel vapor and air during the ring period of the transducer. | 10-06-2011 |
20120000212 | TRANSPORT REFRIGERATION SYSTEM WITH PREDICTIVE REFRIGERATION - A transport unit including a container defining a cargo space. The transport unit includes position detection apparatus coupled to the container, and adapted to determine a geographic location of the container and to generate a signal indicative of the geographic location. The transport unit also includes a refrigeration system in communication with the cargo space, and a control system including route data that defines a plurality of potential destinations of the container. The control system is programmed to predict a container route defined by at least two potential destinations of the container based on the geographic location and the route data, and to determine a proximity of the container relative to at least one potential destination of the route. The control system is in communication with the refrigeration system to control the refrigeration system based on the proximity of the container relative to the at least one potential destination. | 01-05-2012 |
20120261396 | FLUID LEVEL MEASUREMENT SYSTEM AND METHOD - A method for measuring a fluid level in a tank containing a fluid for a transportable temperature controlled space. The method includes providing a temperature control system for the transportable temperature controlled space, providing a fluid level sensor for sensing a fluid level in the tank, generating fluid level signals with the fluid level sensor indicative of the fluid level in the tank, providing a fluid level algorithm for receiving the fluid level signals from the fluid level sensor and computing the fluid level in the tank, and inhibiting nondeterministic fluid level signals from being introduced to the fluid level algorithm. | 10-18-2012 |
20130255910 | VEHICLE OR ENVIRONMENT-CONTROLLED UNIT HAVING A MULTIPHASE ALTERNATOR WITH A PROTECTED HIGH-VOLTAGE BUS - A mobile environment-controlled unit, such as an over-the-road compartment trailer, having an environmental-control system, such as a refrigeration unit, powered by an alternator and having a high-voltage alternating current (AC) bus. The unit incorporates a high resistance ground scheme and can incorporate a solid-state input module to detect phase-chassis faults. This combination provides an improvement in protection for mobile applications that cannot have a voltage reference (or neutral point) solidly connected to earth ground. | 10-03-2013 |
20130257048 | MOBILE ENVIRONMENT-CONTROLLED UNIT HAVING A MAGNETIC SENSOR FOR A HIGH-VOLTAGE ALTERTNATING CURRENT BUS - A mobile unit (e.g., a vehicle or a mobile environment-controlled unit) having a multiphase alternator, such as a three-phase alternator. The unit incorporates a Hall Effect current sensor to monitor all three phases of the high-voltage AC bus from the alternator. | 10-03-2013 |
20140339844 | VEHICLE OR ENVIRONMENT-CONTROLLED UNIT HAVING A MULTIPHASE ALTERNATOR WITH A PROTECTED HIGH-VOLTAGE BUS - A mobile environment-controlled unit, such as an over-the-road compartment trailer, having an environmental-control system, such as a refrigeration unit, powered by an alternator and having a high-voltage alternating current (AC) bus. The unit incorporates a high resistance ground scheme and can incorporate a solid-state input module to detect phase-chassis faults. This combination provides an improvement in protection for mobile applications that cannot have a voltage reference (or neutral point) solidly connected to earth ground. | 11-20-2014 |
20150177047 | FLUID LEVEL MEASUREMENT SYSTEM AND METHOD - A transport refrigeration system for a transportable temperature controlled space includes a compressor, a condenser and an evaporator fluidly connected to one another, an engine operatively connected to the compressor, and a fuel tank assembly fluidly connected to the engine. The fuel tank assembly includes a fuel tank configured to contain the fuel, a fuel vapor and air, and an ultrasonic fluid level sensor for sensing a level of fuel, the fuel tank having a maximum fuel level. The fluid level sensor includes a transducer having a ring period. The distance from the fluid level sensor to the maximum fuel level is at least half the distance that the sound travels through the fuel vapor and air during the ring period of the transducer. | 06-25-2015 |
20150183292 | CURRENT DRAW CONTROL IN A TRANSPORT REFRIGERATON SYSTEM - A system and method for controlling a current draw in a transport refrigeration system (TRS) including an electronically controlled engine having an engine control unit (ECU) are disclosed. The method includes disabling the ECU in response to the electronically controlled engine entering an operating mode in which the electronically controlled engine is not running The TRS controller determines an ambient temperature based on a temperature outside an internal space of the refrigerated transport unit. The TRS controller initializes an ECU off timer when the ambient temperature is less than or equal to an ambient temperature threshold. | 07-02-2015 |
20150188323 | METHOD AND SYSTEM FOR CONFIGURING A TRANSPORT REFRIGERATION UNIT BATTERY CHARGER FOR USE IN A TRANSPORT REFRIGERATION SYSTEM - A system and method for configuring a transport refrigeration unit (TRU) battery charger in a transport refrigeration system (TRS) is provided. The method includes receiving battery topology data indicating a battery topology of a TRU battery equipped in the TRS. The method also includes determining specific parameters for configuring a battery charging algorithm based on the battery topology data. Also, the method includes the TRU battery charger configuring the battery charging algorithm based on the specific parameters. | 07-02-2015 |
20150349548 | OFFSET CURRENT IMPLEMENTATION FOR BATTERY CHARGER - A transport refrigeration unit (TRU) battery charging system includes a programmable transport refrigeration system (TRS) Controller, a TRU battery and a programmable battery charger (BC) programmed to transfer electrical current to the TRU battery via a predetermined current path through the programmable TRS Controller in response to a value of offset current drawn from the TRU battery by the programmable TRS Controller and subsequently communicated to the programmable BC by the programmable TRS Controller. The programmable TRU battery charger allows for a dynamic load characterization of the programmable TRS Controller and accessory loads based on programmable TRU battery charger internal shunt current measurements and programmable TRS Controller internal shunt current measurements to allow the programmable TRU battery charger to function properly with all intended modes of operation. | 12-03-2015 |
20160043543 | VEHICLE OR ENVIRONMENT-CONTROLLED UNIT HAVING A MULTIPHASE ALTERNATOR WITH A PROTECTED HIGH-VOLTAGE BUS - A mobile environment-controlled unit, such as an over-the-road compartment trailer, having an environmental-control system, such as a refrigeration unit, powered by an alternator and having a high-voltage alternating current (AC) bus. The unit incorporates a high resistance ground scheme and can incorporate a solid-state input module to detect phase-chassis faults. This combination provides an improvement in protection for mobile applications that cannot have a voltage reference (or neutral point) solidly connected to earth ground. | 02-11-2016 |
Patent application number | Description | Published |
20120287974 | RECOVERING DATA FROM A PRIMARY ONE OF SIMULTANEOUS SIGNALS, SUCH AS ORTHOGONAL-FREQUENCY-DIVISION-MULTIPLEXED (OFDM) SIGNALS, THAT INCLUDE A SAME FREQUENCY - An embodiment of a receiver includes signal- and data-recovery units. The signal-recovery unit is configured to recover a first component of a first signal that is received simultaneously with a second signal having a second component, the first and second components including approximately a frequency. And the data-recovery unit is configured to recover data from the first signal in response to the recovered first component. For example, such a receiver may be able to receive simultaneously, and over the same channel space, multiple orthogonal-frequency-division-multiplexed (OFDM) signals that include one or more of the same subcarrier frequencies, and to recover data from one or more of the OFDM signals despite the frequency overlap. A receiver with this capability may allow an increase in the effective bandwidth of the channel space, and thus may allow more devices (e.g., smart phones) to simultaneously share the same channel space. | 11-15-2012 |
20120300866 | SIMULTANEOUS TRANSMISSION OF SIGNALS, SUCH AS ORTHOGONAL-FREQUENCY-DIVISION-MULTIPLEXED (OFDM) SIGNALS, THAT INCLUDE A SAME FREQUENCY - An embodiment of a transmitter includes detection, generating, and transmission stages. The detection stage is configured to detect a first signal having a first component that includes a frequency, and the generating stage is configured to generate a data component that includes approximately the frequency in response to the detection of the first signal. The transmission stage is configured to transmit a second signal having the data component while the detection stage is detecting the first signal. For example, two or more such transmitters (e.g., two or more smart phones) may simultaneously transmit OFDM signals on the same subcarrier frequencies and over the same channel space. By allowing the simultaneous transmission of multiple signals on the same frequencies and over the same channel space, such a transmitter may increase the effective bandwidth of the channel space, and thus may allow more devices to simultaneously share the same channel space. | 11-29-2012 |
20130022091 | RECOVERING DATA FROM A SECONDARY ONE OF SIMULTANEOUS SIGNALS, SUCH AS ORTHOGONAL-FREQUENCY-DIVISION-MULTIPLEXED (OFDM) SIGNALS, THAT INCLUDE A SAME FREQUENCY - An embodiment of a receiver includes a channel estimator and a data-recovery unit. The channel estimator is configured to determine a characteristic of a channel over which a first signal, which is received simultaneously with a second signal, propagated, the first and second signals respectively having first and second components that include approximately a frequency. And the data-recovery unit is configured to recover data from the first signal in response to the determined channel characteristic. For example, such a receiver may be able to receive simultaneously, and over the same channel space, orthogonal-frequency-division-multiplexed (OFDM) signals that include one or more of the same subcarrier frequencies, and to recover data from one or more of the OFDM signals despite the frequency overlap. A receiver with this capability may allow an increase in the effective bandwidth of the channel space, and thus may allow more devices to simultaneously share the channel space. | 01-24-2013 |
20140128004 | CONVERTING SAMPLES OF A SIGNAL AT A SAMPLE RATE INTO SAMPLES OF ANOTHER SIGNAL AT ANOTHER SAMPLE RATE - In an embodiment, an apparatus includes a determiner, converter, adapter, and modifier. The determiner is configured to generate a representation of a difference between a first frequency at which a first signal is sampled and a second frequency at which a second signal is sampled, and the converter is configured to generate a second sample of the first signal at a second time in response to the representation and a first sample of the first signal at a first time. The adapter is configured to generate a sample of a modifier signal in response to the second sample of the first signal, and the modifier is configured to generate a modified sample of the second signal in response to a sample of the second signal and the sample of the modifier signal. For example, such an apparatus may be able to reduce the magnitude of an echo signal in a system having an audio pickup (e.g., a microphone) near an audio output (e.g., a speaker). | 05-08-2014 |
Patent application number | Description | Published |
20120173058 | MODULARIZED HYBRID POWER TRAIN CONTROL - A method includes manufacturing a first assembly having an application requirements module that interprets a contemporaneous performance specification, and an energy partitioning module that provides an electric motor torque target, a battery power flux target, and an internal combustion engine torque target. The method further includes manufacturing a second assembly having an engine control module that controls an internal combustion engine in response to the internal combustion engine torque target. The method includes integrating the first assembly and the second assembly with a third assembly to form a completed hybrid power train, where the third assembly includes a datalink that receives the internal combustion engine torque target from the first assembly and provides the internal combustion engine torque target to the second assembly. | 07-05-2012 |
20120208672 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes determining a machine shaft torque demand and a machine shaft speed, in response to the machine shaft torque demand and the machine shaft speed, determining a machine power demand, determining a power division description between an internal combustion engine, a first electrical torque provider, and a second electrical torque provider, determining a hybrid power train configuration as one of series and parallel, determining a baseline power division description in response to a vehicle speed and the machine power demand, determining a state-of-charge (SOC) deviation for an electrical energy storage device electrically coupled to the first electrical torque provider and the second electrical torque provider, and adjusting the baseline power division description in response to the SOC deviation and the hybrid power train configuration. | 08-16-2012 |
20130146374 | HYBRID VEHICLE BRAKING ADJUSTMENT FOR VEHICLE WEIGHT - A method, apparatus, and system are disclosed for hybrid power system braking. In one embodiment, a vehicle weight input is received by a brake controller. In response to receiving the vehicle weight input, a maximum negative braking torque is determined. Regulation of negative braking torque according to vehicle weight is accomplished by one or both of a regenerative braking device and mechanical braking device. | 06-13-2013 |
20130184908 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A system includes a hybrid power train comprising an internal combustion engine and electrical system, which includes a first and second electrical torque provider, and an electrical energy storage device electrically coupled to first and second electrical torque provider. The system further includes a controller structured to perform operations including determining a power surplus value of the electrical system; determining a machine power demand change value; in response to the power surplus value of the electrical system being greater than or equal to the machine power demand change value, operating an optimum cost controller to determine a power division for the engine, first electrical torque provider, and second electrical torque provider; and in response to the power surplus value of the electrical system being less than the machine power demand change value, operating a rule-based controller to determine the power division for the engine, first, and second electrical torque provider. | 07-18-2013 |
20130184909 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes defining an application operating cycle and a number of behavior matrices for a hybrid power train that powers the application, each behavior matrix corresponding to operations of the hybrid power train operating in a parallel configuration. The method includes determining a number of behavior sequences corresponding to the behavior matrices and applied sequentially to the application operating cycle, confirming a feasibility of each of the behavior sequences, determining a fitness value corresponding to each of the feasible behavior sequences, in response to the fitness value determining whether a convergence value indicates that a successful convergence has occurred, and in response to determining that a successful convergence has occurred, determining a calibration matrix in response to the behavior matrices and fitness values. The method includes providing the calibration matrix to a hybrid power train controller. | 07-18-2013 |
20130184910 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes operating a hybrid power train having an internal combustion engine, at least one electrical torque provider, and an electrical energy storage device electrically coupled to the electrical torque provider(s). The method further includes determining a machine power demand, and determining a power division description in response to the machine power demand. The method further includes interpreting a state-of-health (SOH) for the electrical energy storage device, and in response to the SOH for the electrical energy storage device, adjusting the power division description. | 07-18-2013 |
20130184911 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A system includes a hybrid power train including an engine, a first electrical torque provider, and a second electrical torque provider. The system further includes a load mechanically coupled to the hybrid power train. The hybrid power train further includes a clutch coupled to the engine and the second electrical torque provider on a first side, and coupled to the first electrical torque provider and the load on a second side. The system further includes an electrical energy storage device electrically coupled to the electrical torque providers. The system further includes a controller that performs operations to smooth torque commands for the engine and the second electrical torque provider in response to determining that a clutch engage-disengage event occurring or imminent. | 07-18-2013 |
20130184912 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes operating a hybrid power train having an internal combustion engine and an electrical torque provider. The method further includes determining a machine power demand and, in response to the machine power demand, determining a power division description. The method includes operating the internal combustion engine and the electrical torque provider in response to the power division description. The method further includes operating the internal combustion engine by starting the internal combustion engine in response to determining that a battery state-of-charge is below a predetermined threshold value. | 07-18-2013 |
20130184913 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes operating a hybrid power train having an internal combustion engine and at least one electrical torque provider. The method further includes determining a machine power demand for the hybrid power train, and determining a power division between the internal combustion engine and the electrical torque provider in response to the machine power demand. The method further includes determining a state-of-charge (SOC) of an electrical energy storage device electrically coupled to the at least one electrical torque provider and interpreting a target SOC for the electrical energy storage device in response to a vehicle speed, and determining an SOC deviation for the electrical storage device, wherein the SOC deviation comprises a function of a difference between the SOC of the electrical energy storage device and the target SOC of the electrical energy storage device. | 07-18-2013 |
20130184914 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes operating a hybrid power train having an internal combustion engine and an electrical torque provider. The method further includes determining a machine power demand and an audible noise limit value for the internal combustion engine. The method includes determining a power division description in response to the machine power demand and the audible noise limit value, and operating the internal combustion engine and the electrical torque provider in response to the power division description. | 07-18-2013 |
20140222262 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A system includes a hybrid power train comprising an internal combustion engine and electrical system, which includes a first and second electrical torque provider, and an electrical energy storage device electrically coupled to first and second electrical torque provider. The system further includes a controller structured to perform operations including determining a power surplus value of the electrical system; determining a machine power demand change value; in response to the power surplus value of the electrical system being greater than or equal to the machine power demand change value, operating an optimum cost controller to determine a power division for the engine, first electrical torque provider, and second electrical torque provider; and in response to the power surplus value of the electrical system being less than the machine power demand change value, operating a rule-based controller to determine the power division for the engine, first, and second electrical torque provider. | 08-07-2014 |
20140222263 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A system includes a hybrid power train including an engine, a first electrical torque provider, and a second electrical torque provider. The system further includes a load mechanically coupled to the hybrid power train. The hybrid power train further includes a clutch coupled to the engine and the second electrical torque provider on a first side, and coupled to the first electrical torque provider and the load on a second side. The system further includes an electrical energy storage device electrically coupled to the electrical torque providers. The system further includes a controller that performs operations to smooth torque commands for the engine and the second electrical torque provider in response to determining that a clutch engage-disengage event occurring or imminent. | 08-07-2014 |
20140222264 | SYSTEM, METHOD, AND APPARATUS FOR CONTROLLING POWER OUTPUT DISTRIBUTION IN A HYBRID POWER TRAIN - A method includes operating a hybrid power train having an internal combustion engine and an electrical torque provider. The method further includes determining a machine power demand and an audible noise limit value for the internal combustion engine. The method includes determining a power division description in response to the machine power demand and the audible noise limit value, and operating the internal combustion engine and the electrical torque provider in response to the power division description. | 08-07-2014 |
20150142229 | HYBRID CONTROLS ARCHITECTURE - Apparatuses, methods and systems for hybrid powertrain control are disclosed. Certain example embodiments control an internal combustion engine and a motor/generator of a hybrid electric powertrain. Example controls may determine a total output demanded of a powertrain based at least in part upon an operator input, a battery output target based upon a battery state of charge and independent of the operator input, and an engine output target based upon the total output demanded and the battery output target. Such example controls may further determine a constrained engine output target, a modified battery output target based upon the total output demanded and the constrained engine output target, and a constrained battery output target based upon the modified battery output target and a battery constraint. Further embodiments, forms, objects, features, advantages, aspects, and benefits shall become apparent from the following description and figures. | 05-21-2015 |
20150252770 | ENGINE START/STOP FUNCTION MANAGEMENT AND CONTROL ARCHITECTURE - Unique apparatuses, systems, methods, and techniques for control of engine systems are disclosed. One embodiment is a unique controls process providing engine start/stop functionality. In one form, the controls process includes engine stop controls which evaluate a plurality of engine stop request conditions and a plurality of engine stop capability conditions, as well as engine start controls which evaluate a plurality of engine start request conditions and a plurality of engine start capability conditions. | 09-10-2015 |
Patent application number | Description | Published |
20090080442 | CONSERVING POWER IN A MULTI-NODE ENVIRONMENT - A coordinated mechanism to conserve power in a multi-node environment is disclosed. A multi-node environment may comprise multiple individual computer systems coupled by a network or, a shared memory architecture multiprocessors, or many-core computers. The power management features of the processor, platform elements, and the devices may be used to conserve power in a multi-node environment. A master node may determine the task and slave nodes required to perform the task and may wake-up the slave nodes required to perform the task while causing the other slave nodes to enter or continue in the sleep-state. The slave nodes, which are woken in-turn may determine the components of the slave nodes required for performing the assigned task and may cause other components to enter a sleep-state. | 03-26-2009 |
20120102348 | FINE GRAINED POWER MANAGEMENT IN VIRTUALIZED MOBILE PLATFORMS - A system and method of managing power may include determining a power state based on a first power management request from a first operating system executing on a mobile platform and a second power management request from a second operating system executing on the mobile platform. The first operating system and one or more components of the mobile platform can define a first virtual machine, and the second operating system and one or more components of the mobile platform can define a second virtual machine. In addition, the power state may be applied to the mobile platform. | 04-26-2012 |
20120166779 | METHOD, APPARATUS AND SYSTEM TO SAVE PROCESSOR STATE FOR EFFICIENT TRANSITION BETWEEN PROCESSOR POWER STATES - Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment. | 06-28-2012 |
20120166843 | METHOD, APPARATUS AND SYSTEM TO TRANSITION SYSTEM POWER STATE OF A COMPUTER PLATFORM - Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states. | 06-28-2012 |
20120167109 | FRAMEWORK FOR RUNTIME POWER MONITORING AND MANAGEMENT - Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform. | 06-28-2012 |
20130138985 | POWER MANAGEMENT USING RELATIVE ENERGY BREAK-EVEN TIME - Systems and methods may provide for determining an absolute energy break-even time for a first low power state with respect to a current state of a system. A relative energy break-even time may also be determined for the first low power state with respect to a second low power state based on at least in part the absolute energy break-even time. In addition, an operating state may be selected for the system based on at least in part the relative energy break-even time. | 05-30-2013 |
20140181560 | PLATFORM POWER CONSUMPTION REDUCTION VIA POWER STATE SWITCHING - Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed. | 06-26-2014 |
20140258749 | DYNAMICALLY ENTERING LOW POWER STATES DURING ACTIVE WORKLOADS - Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination. | 09-11-2014 |
20150121114 | FRAMEWORK FOR RUNTIME POWER MONITORING AND MANAGEMENT - Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform. | 04-30-2015 |
Patent application number | Description | Published |
20090085023 | PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater comprises a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer. | 04-02-2009 |
20090085024 | PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers. | 04-02-2009 |
20110001113 | PHASE CHANGE MEMORY STRUCTURES - A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers. | 01-06-2011 |
20110053361 | FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer - A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer ( | 03-03-2011 |
20110117712 | SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE - A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region. | 05-19-2011 |
20110269276 | METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES - In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer. | 11-03-2011 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 02-16-2012 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 02-16-2012 |
20120181549 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers. | 07-19-2012 |
20120261672 | MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS - A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications. | 10-18-2012 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 11-15-2012 |
20120306017 | WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS - An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET). | 12-06-2012 |
20130032865 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 02-07-2013 |
20130032883 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 02-07-2013 |
20130119473 | GATE STRUCTURES AND METHODS OF MANUFACTURE - A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material. | 05-16-2013 |
20130140636 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers. | 06-06-2013 |
20130288440 | MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS - A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications. | 10-31-2013 |
20140159162 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140159163 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140367748 | EXTENDED GATE SENSOR FOR pH SENSING - A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well. | 12-18-2014 |
20140370636 | EXTENDED GATE SENSOR FOR pH SENSING - A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well. | 12-18-2014 |
20150014782 | GATE STRUCTURES AND METHODS OF MANUFACTURE - A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material. | 01-15-2015 |
20150236118 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 08-20-2015 |
20150347922 | MULTI-MODEL BLENDING - A method and a system to perform multi-model blending are described. The method includes obtaining one or more sets of predictions of historical conditions, the historical conditions corresponding with a time T that is historical in reference to current time, and the one or more sets of predictions of the historical conditions being output by one or more models. The method also includes obtaining actual historical conditions, the actual historical conditions being measured conditions at the time T, assembling a training data set including designating the two or more set of predictions of historical conditions as predictor variables and the actual historical conditions as response variables, and training a machine learning algorithm based on the training data set. The method further includes obtaining a blended model based on the machine learning algorithm. | 12-03-2015 |