Patent application number | Description | Published |
20080237684 | Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field - A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed. | 10-02-2008 |
20090040841 | Method of Operating an Integrated Circuit Having at Least One Memory Cell - Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state. | 02-12-2009 |
20090154264 | Integrated circuits, memory controller, and memory modules - In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level. | 06-18-2009 |
20090185441 | Integrated Circuit and Method to Operate an Integrated Circuit - Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation. | 07-23-2009 |
20090190408 | Method of Operating an Integrated Circuit, Integrated Circuit and Method to Determine an Operating Point - Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to determine an operating point of an integrated circuit. | 07-30-2009 |
20090244949 | Memory Device and Method Providing Logic Connections for Data Transfer - In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections. | 10-01-2009 |
20110308602 | SOLAR CELL, SOLAR CELL MANUFACTURING METHOD AND TESTING METHOD - A solar cell includes a semiconductor substrate and an antireflection layer arranged on the light incidence side on the front-side surface of a semiconductor substrate. The antireflection layer has a limit voltage of less than 10 volts, less than 5 volts, or less than 3 volts, along a layer thickness of the antireflection layer. | 12-22-2011 |