Patent application number | Description | Published |
20080246136 | Chips having rear contacts connected by through vias to front contacts - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 10-09-2008 |
20090115047 | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements - An interconnect element | 05-07-2009 |
20090160065 | Reconstituted Wafer Level Stacking - A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique. | 06-25-2009 |
20090212381 | WAFER LEVEL PACKAGES FOR REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS - A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to receive light through the part of the rear face within the recess. A solid state image sensor can include a microelectronic element having a front face and a rear face remote from the front face, a plurality of light sensing elements disposed adjacent to the front face, the light sensing elements being arranged to receive light through the rear face. Electrically conductive package contacts may directly overlie the light sensing elements and the front face and be connected to chip contacts at the front face through openings in an insulating packaging layer overlying the front face. | 08-27-2009 |
20100053407 | Wafer level compliant packages for rear-face illuminated solid state image sensors - A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to receive light through the part of the rear face within the recess. A solid state image sensor can include a microelectronic element, e.g., a semiconductor chip, having a front face and a rear face remote from the front face, a plurality of light sensing elements disposed adjacent to the front face, the light sensing elements being arranged to receive light through the rear face. A packaging structure, which can include a compliant layer, can be attached to a front surface of the microelectronic element. Electrically conductive package contacts may directly overlie the light sensing elements and the front face and be connected to chip contacts at the front face through openings in an insulating packaging layer overlying the front face. | 03-04-2010 |
20100225006 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 09-09-2010 |
20100230812 | Microelectronic Assemblies Having Compliancy and Methods Therefor - A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces. | 09-16-2010 |
20110012259 | PACKAGED SEMICONDUCTOR CHIPS - A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device. | 01-20-2011 |
20110031629 | EDGE CONNECT WAFER LEVEL STACKING - In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies. | 02-10-2011 |
20110033979 | EDGE CONNECT WAFER LEVEL STACKING - A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package. | 02-10-2011 |
20110049696 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 03-03-2011 |
20110187007 | EDGE CONNECT WAFER LEVEL STACKING - A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly. | 08-04-2011 |
20120018863 | MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES - A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel. | 01-26-2012 |
20120018868 | MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVERLYING VIAS - A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element. | 01-26-2012 |
20120018893 | METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM - A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device. | 01-26-2012 |
20120018894 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 01-26-2012 |
20120018895 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 01-26-2012 |
20120020026 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit includes a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can include a microelectronic element having a bottom surface adjacent the inner surface, a top surface remote from the bottom surface, and a plurality of contacts at the top surface. The microelectronic element can include terminals electrically connected with the contacts of the microelectronic element. The microelectronic unit can include a dielectric region contacting at least the top surface of the microelectronic element. The dielectric region can have a planar surface located coplanar with or above the front surface of the carrier structure. The terminals can be exposed at the surface of the dielectric region for interconnection with an external element. | 01-26-2012 |
20120068327 | MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 03-22-2012 |
20120068330 | STAGED VIA FORMATION FROM BOTH SIDES OF CHIP - A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad. | 03-22-2012 |
20120068351 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 03-22-2012 |
20120068352 | STACKED CHIP ASSEMBLY HAVING VERTICAL VIAS - An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region. | 03-22-2012 |
20120139082 | STACKED MICROELECTRONIC ASSEMBY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 06-07-2012 |
20120139094 | STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS - A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element. In one example, one or more of the first or second conductive elements extends through the respective first or second pad, and the conductive elements contact the exposed portions of the second conductive element to provide electrical connection therewith. | 06-07-2012 |
20120139124 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 06-07-2012 |
20120146182 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. | 06-14-2012 |
20120146210 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 06-14-2012 |
20120152433 | DUAL WAFER SPIN COATING - A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates. | 06-21-2012 |
20120153426 | VOID-FREE WAFER BONDING USING CHANNELS - A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels. | 06-21-2012 |
20120153488 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 06-21-2012 |
20120199924 | BSI IMAGE SENSOR PACKAGE WITH VARIABLE LIGHT TRANSMISSION FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a semiconductor region adjacent a rear face. The semiconductor region has a first region of material overlying the first light sensing element and a second region of material overlying the second light sensing element such that the first and second wavelengths are able to pass through the first and second regions, respectively, and reach the first and second light sensing elements with substantially the same intensity. | 08-09-2012 |
20120326313 | SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS - Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed. | 12-27-2012 |
20120326326 | Systems and Methods for Producing Flat Surfaces in Interconnect Structures - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 12-27-2012 |
20130014978 | Electrical Barrier LayersAANM Uzoh; CyprianAACI San JoseAAST CAAACO USAAGP Uzoh; Cyprian San Jose CA USAANM Oganesian; VageAACI Palo AltoAAST CAAACO USAAGP Oganesian; Vage Palo Alto CA USAANM Mohammed; IlyasAACI Santa ClaraAAST CAAACO USAAGP Mohammed; Ilyas Santa Clara CA USAANM Haba; BelgacemAACI SaratogaAAST CAAACO USAAGP Haba; Belgacem Saratoga CA USAANM Savalia; PiyushAACI Santa ClaraAAST CAAACO USAAGP Savalia; Piyush Santa Clara CA USAANM Mitchell; CraigAACI San JoseAAST CAAACO USAAGP Mitchell; Craig San Jose CA US - Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer. | 01-17-2013 |
20140057370 | DUAL WAFER SPIN COATING - A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates. | 02-27-2014 |