Patent application number | Description | Published |
20080246131 | CHIP PACKAGE STRUCTURE - A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components. | 10-09-2008 |
20080258279 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 10-23-2008 |
20080303174 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 12-11-2008 |
20100187691 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20100187692 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20110133322 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 06-09-2011 |
20110136299 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 06-09-2011 |
Patent application number | Description | Published |
20080265397 | Chip-Stacked Package Structure - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer. | 10-30-2008 |
20080265400 | Chip-Stacked Package Structure and Applications Thereof - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer. | 10-30-2008 |
20100155929 | Chip-Stacked Package Structure - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer. | 06-24-2010 |
Patent application number | Description | Published |
20110156281 | Quad Flat No Lead (QFN) Package - The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention. | 06-30-2011 |
20120091570 | CHIP PACKAGE STRUCTURE AND CHIP PACKAGING METHOD - A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening. | 04-19-2012 |
20120241935 | PACKAGE-ON-PACKAGE STRUCTURE - A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps. | 09-27-2012 |
20130020688 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe. | 01-24-2013 |
20130140686 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar. | 06-06-2013 |
20150076670 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires. | 03-19-2015 |