Patent application number | Description | Published |
20090090952 | PLASMA SURFACE TREATMENT FOR SI AND METAL NANOCRYSTAL NUCLEATION - A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide. | 04-09-2009 |
20100224130 | ROTATING SUBSTRATE SUPPORT AND METHODS OF USE - A method and apparatus for processing a substrate utilizing a rotating substrate support are disclosed herein. In one embodiment, an apparatus for processing a substrate includes a chamber having a substrate support assembly disposed within the chamber. The substrate support assembly includes a substrate support having a support surface and a heater disposed beneath the support surface. A shaft is coupled to the substrate support and a motor is coupled to the shaft through a rotor to provide rotary movement to the substrate support. A seal block is disposed around the rotor and forms a seal therewith. The seal block has at least one seal and at least one channel disposed along the interface between the seal block and the shaft. A port is coupled to each channel for connecting to a pump. A lift mechanism is coupled to the shaft for raising and lowering the substrate support. | 09-09-2010 |
20120291709 | ROTATING SUBSTRATE SUPPORT AND METHODS OF USE - A method and apparatus for processing a substrate utilizing a rotating substrate support are disclosed herein. In one embodiment, an apparatus for processing a substrate includes a chamber having a substrate support assembly disposed within the chamber. The substrate support assembly includes a substrate support having a support surface and a heater disposed beneath the support surface. A shaft is coupled to the substrate support and a motor is coupled to the shaft through a rotor to provide rotary movement to the substrate support. A seal block is disposed around the rotor and forms a seal therewith. The seal block has at least one seal and at least one channel disposed along the interface between the seal block and the shaft. A port is coupled to each channel for connecting to a pump. A lift mechanism is coupled to the shaft for raising and lowering the substrate support. | 11-22-2012 |
20130233378 | HIGH-EFFICIENCY PHOTOVOLTAIC BACK-CONTACT SOLAR CELL STRUCTURES AND MANUFACTURING METHODS USING SEMICONDUCTOR WAFERS - A back contact back junction solar cell using semiconductor wafers and methods for manufacturing are provided. The back contact back junction solar cell comprises a semiconductor wafer having a doped base region, a light capturing frontside surface, and a doped backside emitter region. A frontside and backside dielectric layer and passivation layer provide enhance light trapping and internal reflection. Backside base and emitter contacts are connected to metal interconnects forming a metallization pattern of interdigitated fingers and busbars on the backside of the solar cell. | 09-12-2013 |
20140033971 | HIGH PRODUCTIVITY SPRAY PROCESSING FOR SEMICONDUCTOR METALLIZATION AND INTERCONNECTS - Processing equipment for the metallization of a plurality of workpieces are provided. The equipment comprising a controlled atmospheric region isolated from external oxidizing ambient with at least one deposition zone for the application of a metal layer on a workpiece. A transport system moves the workpiece positioned in a batch carrier plate through the controlled atmospheric region. | 02-06-2014 |
20140038392 | SYSTEMS AND METHODS FOR LASER SPLITTING AND DEVICE LAYER TRANSFER - Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation. | 02-06-2014 |
20150020877 | HIGH-EFFICIENCY SOLAR PHOTOVOLTAIC CELLS AND MODULES USING THIN CRYSTALLINE SEMICONDUCTOR ABSORBERS - Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described. | 01-22-2015 |
Patent application number | Description | Published |
20080197125 | SUBSTRATE HEATING METHOD AND APPARATUS - Embodiments of substrate heating methods and apparatus are provided herein. In one embodiment, a substrate heater is provided including a heater plate having a top surface and an opposing bottom surface, a recess formed in the top surface, the recess having a feature having an upper surface for supporting a substrate, wherein the depth from a bottom surface of the recess to the upper surface of the feature is at least 5 mils. One or more pads may be disposed in the recess for supporting a substrate. The heater plate may have a thickness of about 19 mm. One or more indentations may be formed in the bottom surface of the recess for altering the rate of heat transfer to a portion of a substrate disposed above the indentation during processing. The heater plate may be utilized in a process chamber for performing heat-assisted processes. | 08-21-2008 |
20090111284 | METHOD FOR SILICON BASED DIELECTRIC CHEMICAL VAPOR DEPOSITION - Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes heating a substrate disposed in a processing chamber to a temperature less than about 550 degrees Celsius; flowing a nitrogen and carbon containing chemical comprising (H | 04-30-2009 |
20090314762 | Multi-Zone Resistive Heater - Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support a substrate, a shaft coupled to the stage, a first heating element disposed within a central region of the body of the stage, and at least second and third heating elements disposed within the body of the stage, the at least second and third heating elements each partially surrounding the first heating element and wherein the at least second and third heating elements are circumferentially adjacent to each other. | 12-24-2009 |
20100294199 | CVD APPARATUS FOR IMPROVED FILM THICKNESS NON-UNIFORMITY AND PARTICLE PERFORMANCE - Embodiments of the invention provide improved apparatus for depositing layers on substrates, such as by chemical vapor deposition (CVD). The inventive apparatus disclosed herein may advantageously facilitate one or more of depositing films having reduced film thickness non-uniformity within a given process chamber, improved particle performance (e.g., reduced particles on films formed in the process chamber), chamber-to-chamber performance matching amongst a plurality of process chambers, and improved process chamber serviceability. | 11-25-2010 |
20110101442 | Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control - A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed. | 05-05-2011 |
20110281429 | Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control - A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed. | 11-17-2011 |
20110284068 | PASSIVATION METHODS AND APPARATUS FOR ACHIEVING ULTRA-LOW SURFACE RECOMBINATION VELOCITIES FOR HIGH-EFFICIENCY SOLAR CELLS - The disclosed subject matter provides a method and structure for obtaining ultra-low surface recombination velocities from highly efficient surface passivation in crystalline silicon substrate-based solar cells by utilizing a bi-layer passivation scheme which also works as an efficient ARC. The bi-layer passivation consists of a first thin layer of wet chemical oxide or a thin hydrogenated amorphous silicon layer. A second layer of amorphous hydrogenated silicon nitride film is deposited on top of the wet chemical oxide or amorphous silicon film. This deposition is then followed by annealing to further enhance the surface passivation. | 11-24-2011 |
20120103408 | BACKPLANE REINFORCEMENT AND INTERCONNECTS FOR SOLAR CELLS - Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects. | 05-03-2012 |
20120305063 | HIGH-EFFICIENCY PHOTOVOLTAIC BACK-CONTACT SOLAR CELL STRUCTURES AND MANUFACTURING METHODS USING THIN PLANAR SEMICONDUCTOR ABSORBERS - Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell. | 12-06-2012 |
20130000715 | ACTIVE BACKPLANE FOR THIN SILICON SOLAR CELLS - Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, attaching a prepeg backplane to the interdigitated pattern of base electrodes and emitter electrodes, forming holes in the prepeg backplane which provide access to the first layer of electrically conductive metal, and depositing a second layer of electrically conductive metal on the backside surface of the prepeg backplane forming an electrical interconnect with the first layer of electrically conductive metal through the holes in the prepeg backplane. | 01-03-2013 |
20130164883 | LASER ANNEALING APPLICATIONS IN HIGH-EFFICIENCY SOLAR CELLS - Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. | 06-27-2013 |
20130167915 | HIGH-EFFICIENCY PHOTOVOLTAIC BACK-CONTACT SOLAR CELL STRUCTURES AND MANUFACTURING METHODS USING THREE-DIMENSIONAL SEMICONDUCTOR ABSORBERS - Back contact back junction three dimensional solar cell and methods for manufacturing are provided. The back contact back contact back junction three dimensional solar cell comprises a three-dimensional substrate. The substrate comprises a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer is positioned on the doped backside emitter region. Backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of three-dimensional solar cell. | 07-04-2013 |
20130213469 | HIGH EFFICIENCY SOLAR CELL STRUCTURES AND MANUFACTURING METHODS - Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided. | 08-22-2013 |
20140158193 | STRUCTURES AND METHODS OF FORMATION OF CONTIGUOUS AND NON-CONTIGUOUS BASE REGIONS FOR HIGH EFFICIENCY BACK-CONTACT SOLAR CELLS - Fabrication methods and structures relating to back contact solar cells having patterned emitter and non-nested base regions are provided. | 06-12-2014 |
20140360567 | BACK CONTACT SOLAR CELLS USING ALUMINUM-BASED ALLOY METALLIZATION - Methods and structures for photovoltaic back contact solar cells having multi-level metallization with at least one aluminum-silicon alloy metallization layer are provided. | 12-11-2014 |