Lin, Pleasanton
Allan Ming-Lun Lin, Pleasanton, CA US
Patent application number | Description | Published |
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20100202165 | Dynamic Drive of Switching Transistor of Switching Power Converter - A switching power converter comprises a transformer ( | 08-12-2010 |
20100277104 | 1-WIRE COMMUNICATION PROTOCOL AND INTERFACE CIRCUIT - A 1-wire communication protocol and interface circuitry for communication between a host controller and a LED driver is provided. The 1-wire communication protocol is configured such that both PWM signals and DC current setting commands for programming the LED driver may be transmitted from the host controller to the LED driver via the same 1-wire interface. The 1-wire communication protocol uses the length of the pulses (pulse width), rather than the number of pulses, to distinguish between different modes of communication (PWM signal transmission mode or command pulse transmission mode) and different commands of the same type (specific DC current programming commands, or specific average PWM drive current for the LED, within each transmission mode). Because the same 1-wire interface is used for transmitting both PWM signals and DC current commands, integrated circuits for the host controller and the LED driver do not require an additional wire or pin. | 11-04-2010 |
20130028338 | 1-Wire Communication Protocol and Interface Circuit for High Voltage Applications - A system for communicating with a host using control signals over a 1-wire interface is disclosed. The system includes a driver coupled to the host by the 1-wire interface. Control signals are transmitted from the host to the driver for decoding by the driver controller. The control signals are pulse width modulation format signals which are interpreted by the driver as binary encoded command mode signals or analog encoded command mode signals, depending upon when the signals are received in relation to a preamble pulse and a post-amble pulse. | 01-31-2013 |
20130279209 | DYNAMIC DRIVE OF SWITCHING TRANSISTOR OF SWITCHING POWER CONVERTER - The drive current of the switch in a switching power converter is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the switch drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the switch drive current. | 10-24-2013 |
I Chung Joseph Lin, Pleasanton, CA US
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20130018930 | PEER-TO-PEER REDUNDANT FILE SERVER SYSTEM AND METHODS - Peer-to-peer redundant file server system and methods include clients that determine a target storage provider to contact for a particular storage transaction based on a pathname provided by the filesystem and a predetermined scheme such as a hash function applied to a portion of the pathname. Servers use the same scheme to determine where to store relevant file information so that the clients can locate the file information. The target storage provider may store the file itself and/or may store metadata that identifies one or more other storage providers where the file is stored. A file may be replicated in multiple storage providers, and the metadata may include a list of storage providers from which the clients can select (e.g., randomly) in order to access the file. | 01-17-2013 |
Mei-Lin Lin, Pleasanton, CA US
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20150134678 | Multi-Pass, Parallel Merge for Partitioned Intermediate Pages - Multi-pass parallel merging in a database includes identifying characteristics of non-final pages during database query operations. A phase of page consolidation is triggered based on the identified characteristics and a final page is stored. | 05-14-2015 |
Mei-Ling Lin, Pleasanton, CA US
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20150134900 | CACHE EFFICIENCY IN A SHARED DISK DATABASE CLUSTER - Disclosed herein are system, method, and computer program product embodiments for storing and accessing data in a shared disk database system using a timestamp range to improve cache efficiency. An embodiment operates by retrieving, by a node, from a shared storage. a blockmap identity and a root page associated with a data request, based on a determination that the blockmap identity associated with a data request is present in a cache. The embodiment continues, retrieving, by the node, the logical page by copying a stored logical page from the shared storage and setting a lower timestamp value of the logical page to a timestamp associated with the stored logical page and an upper timestamp value of the logical page to a timestamp associated with the data request, based on a determination that the logical page is not present in the cache. | 05-14-2015 |
Yan Lin, Pleasanton, CA US
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20140181773 | SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRID (PG) ALIGNMENT - Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping. | 06-26-2014 |
20140189629 | PATTERN-BASED POWER-AND-GROUND (PG) ROUTING AND VIA CREATION - Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules. | 07-03-2014 |