Patent application number | Description | Published |
20130100108 | LIQUID CRYSTAL DISPLAY AND DISPLAY DRIVING METHOD THEREOF - A liquid crystal display includes a date line for transmitting a data signal, a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a first sub-pixel unit for being written to by a first sub-pixel voltage according to the data signal and the first gate signal, a second sub-pixel unit for being written to by a second sub-pixel voltage according to the data signal and the first gate signal, a third sub-pixel unit for being written to by a third sub-pixel voltage according to the data signal and the first gate signal, and a charge sharing control unit. The charge sharing control unit is utilized for controlling a charge sharing operation over the first and third sub-pixel units according to the second gate signal, thereby adjusting the first and third sub-pixel voltages. | 04-25-2013 |
20130128166 | DISPLAY PANEL AND PIXEL THEREIN, AND DRIVING METHOD IN DISPLAY PANEL - A pixel includes sub-pixels each of which includes a first display region, a second display region, a third display region, a first capacitor, and a second capacitor. The first capacitor connects the second display region with the third display region. The second capacitor connects the first display region to the third display region via a switch. When the switch is activated, the potential of the third display region is decreased via the second capacitor, the potential of the first display region is increased via the second capacitor, and the potential of the second display region is decreased via the first capacitor. A display panel and driving method in a display panel are also disclosed herein. | 05-23-2013 |
20130155056 | DISPLAY PANEL - Pixel structural designs on a display panel are disclosed. Each pixel on the display panel includes a plurality of sub-pixels. The sub-pixels are arranged sequentially along a vertical direction and used for displaying different colors in a circle. The display panel in the disclosure can be switched between a two-dimensional mode and a three-dimensional mode. In the three-dimensional mode, parts of the sub-pixels are disabled for forming a shielding area. Other adjacent sub-pixels form a pixel displaying unit. | 06-20-2013 |
20130256707 | ARRAY SUBSTRATE AND PIXEL UNIT OF DISPLAY PANEL - An array substrate and a pixel unit of a display panel include a plurality of subpixels arranged in a pixel array (N row*M column). Only one data line is disposed in a portion of two adjacent columns of subpixels in the pixel array, and two data lines are disposed in another portion of two adjacent columns of subpixels in the pixel array. | 10-03-2013 |
20140035968 | PIXEL CIRCUIT, PIXEL STRUCTURE, 2D AND 3D SWITCHABLE DISPLAY DEVICE AND DISPLAY DRIVING METHOD THEREOF - A two-dimension (2D) and three-dimension (3D) switchable display device and display driving method thereof are provided. Each pixel unit of the 2D and 3D switchable display device includes a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel, driven by a first gate line, has a first sub-pixel voltage, and the third sub-pixel, driven by a second gate line, has a third sub-pixel voltage different from the first sub-pixel voltage. The charge of the second sub-pixel is shared by a first gate line of an adjacent pixel unit, and the second sub-pixel has a second sub-pixel voltage different from the first sub-pixel voltage and the third sub-pixel voltage. The first sub-pixel, the second sub-pixel and the third sub-pixel of the pixel unit can be driven in a pre-charge driving manner. | 02-06-2014 |
Patent application number | Description | Published |
20100201903 | FLAT DISPLAY PANEL AND METHOD OF REPAIRING CONDUCTIVE LINES THEREOF - A flat display panel includes a plurality of bridge lines disposed between adjacent common lines. When a short defect occurs, the common line near the short defect can be directly cut off in order to repair the short defect and the common voltage can be transferred through the bridge lines to maintain the normal operation of the flat display panel. | 08-12-2010 |
20120200819 | FLAT DISPLAY PANEL AND METHOD OF REPAIRING THE SAME - A flat display panel includes a bridge line disposed between adjacent common lines. When a short defect occurs, the common line near the short defect can be directly cut off in order to repair the short defect and the common voltage can be transferred through the bridge line to maintain the normal operation of the flat display panel. | 08-09-2012 |
20130336003 | BACKLIGHT MODULE - A backlight module is disclosed in the present invention. The backlight module includes a light guiding plate, a light source, a transformer and a constrainer. The transformer is disposed between the light guiding plate and the light source. The transformer is for transforming a first beam emitted from the light source into a second beam, so as to transmit the second beam to the light guiding plate, wherein a spectrum of the first beam is different from a spectrum of the second beam. The constrainer is connected to the light source for constraining a movement of the transformer. The constrainer includes a first fixing portion disposed on the light source and a second fixing portion connected to the first fixing portion, the second fixing portion being disposed on the transformer to fix the transformer relative to the light source. | 12-19-2013 |
Patent application number | Description | Published |
20140375343 | SOLAR CELL MODULE EFFICACY MONITORING SYSTEM AND MONITORING METHOD THEREFOR - A solar cell module efficacy monitoring system includes a reference module which includes a solar power generation module and is to be maintained in a clean condition, an evaluation module which includes a solar power generation module and is to be covered by dust in an environment, maximum power point tracking devices which track powers of the reference module and the evaluation module and maintain power outputs at maximum points by connected to the reference module and the evaluation module, respectively, and, a PV communication recording device which records power generation results of the reference module and the evaluation module by connected to the reference module and the evaluation module, and a calculation display device which calculates power loss due to accumulation of dust on the evaluation module by connected to the PV communication recording device. | 12-25-2014 |
20150088440 | SOLAR POWER GENERATION MONITORING METHOD AND SOLAR POWER GENERATION MONITORING SYSTEM - A method for monitoring solar power generation includes calculating a cable loss, calculating a maximum power point tracking loss, calculating an inverter loss, calculating a system output coefficient, performing comprehensive calculation based on a rated output power of a solar cell array, a temperature coefficient of the solar cell array, a numerical value of a voltage-current measuring device, a numerical value of a actinometer, a numerical value of a thermometer and a numerical value of a AC power meter such that a module temperature loss is calculated, performing comprehensive calculation based on the cable loss, the maximum power point tracking loss, the inverter loss, the system output coefficient and the module temperature loss such that a module loss is calculated, and displaying and monitoring the cable loss, the maximum power point tracking loss, the inverter loss, the module temperature loss and the module loss. | 03-26-2015 |
20150357973 | SOLAR CELL MODULE EFFICACY MONITORING SYSTEM AND MONITORING METHOD THEREFOR - A solar cell module efficacy monitoring system includes a reference module which includes a solar power generation module and is to be maintained in a clean condition, an evaluation module which includes a solar power generation module and is to be covered by dust in an environment, maximum power point tracking devices which track powers of the reference module and the evaluation module and maintain power outputs at maximum points by connected to the reference module and the evaluation module, respectively, and, a PV communication recording device which records power generation results of the reference module and the evaluation module by connected to the reference module and the evaluation module, and a calculation display device which calculates power loss due to accumulation of dust on the evaluation module by connected to the PV communication recording device. | 12-10-2015 |
Patent application number | Description | Published |
20130181300 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 07-18-2013 |
20130187206 | FinFETs and Methods for Forming the Same - A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions. | 07-25-2013 |
20130228876 | FinFET Design with LDD Extensions - System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions. | 09-05-2013 |
20130341731 | Substrate Resistor and Method of Making Same - A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate. | 12-26-2013 |
20140103453 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 04-17-2014 |
20150155208 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 06-04-2015 |
Patent application number | Description | Published |
20140048929 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 02-20-2014 |
20140077394 | Wafer Level Embedded Heat Spreader - Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads. | 03-20-2014 |
20140097532 | Thermally Enhanced Package-on-Package (PoP) - A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip. | 04-10-2014 |
20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
20150371964 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-24-2015 |
Patent application number | Description | Published |
20120091559 | Capacitor and Method for Making Same - A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth. | 04-19-2012 |
20130020678 | Semiconductor Devices with Orientation-Free Decoupling Capacitors and Methods of Manufacture Thereof - Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented. | 01-24-2013 |
20140042590 | Metal-Insulator-Metal Capacitor and Method of Fabricating - Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors. | 02-13-2014 |
20140091426 | Capacitor and Method for Making Same - A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth. | 04-03-2014 |
20150294936 | MIM CAPACITOR STRUCTURE - The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication. | 10-15-2015 |
20150295019 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor. | 10-15-2015 |
20150295020 | MIM CAPACITOR STRUCTURE - The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer. | 10-15-2015 |
20160071920 | Metal-Insulator-Metal Capacitor with Current Leakage Protection - A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges. | 03-10-2016 |
Patent application number | Description | Published |
20090174833 | PIXEL STRUCTURE AND METHOD OF MAKING THE SAME - A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line. | 07-09-2009 |
20100171687 | DISPLAY DEVICE HAVING SLIM BORDER-AREA ARCHITECTURE AND DRIVING METHOD THEREOF - A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines. | 07-08-2010 |
20100188378 | DISPLAY DEVICE AND METHOD OF EQUALIZING LOADING EFFECT OF DISPLAY DEVICE - A display device includes a substrate, gate lines, data lines, gate tracking lines, and dummy gate tracking lines. The gate lines and the data lines are arranged perpendicularly. Each gate tracking line is disposed between one parts of two adjacent data lines, and substantially parallel to the data lines. Each dummy gate tracking line is electrically disconnected to the gate lines, disposed between other parts of two adjacent data lines, and substantially parallel to the data lines. | 07-29-2010 |
20110169787 | Display Device and Display Driving Method - An exemplary display device includes multiple pixels, first through third gate lines and a data line. The pixels include first through third pixels. The first through third gate lines respectively are electrically coupled with the first through third pixels and for deciding whether to enable the first through third pixels. The first pixel is electrically coupled to the data line to receive a display data provided by the data line. The second pixel is electrically coupled to the first pixel to receive a display data provided by the data line through the first pixel. The third pixel is electrically coupled to the second pixel to receive a display data provided by the data line through both the first pixel and the second pixel. A display driving method adapted to be implemented in the display device also is provided. | 07-14-2011 |
20130113686 | DISPLAY DEVICE - A display device includes a substrate, a plurality of pixels, a plurality of gate lines, and a plurality of data lines. The plurality of pixels is formed on the substrate. The plurality of gate lines is formed on the substrate and for deciding whether to enable the pixels. The plurality of data lines is formed on the substrate and intersecting with the gate lines and for supplying display data to the pixels. Each two neighboring ones of at least a part of the data lines has one or multiple gate fan-out lines arranged therebetween, and each of the gate fan-out lines is electrically coupled to a corresponding one of the gate lines and for supplying driving signals to the corresponding gate line. | 05-09-2013 |