Patent application number | Description | Published |
20120319206 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon. | 12-20-2012 |
20130026546 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench including an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer including nitrogen or carbon. | 01-31-2013 |
20130056845 | METHOD FOR FORMING AN ISOLATION TRENCH - A method forms at least one isolation trench in a substrate having an upper surface. The method includes at least: forming, across the substrate thickness, at least one first cavity opened towards the upper surface; totally filling this first cavity with a dielectric material of a first type; forming a second cavity in an upper portion of the first cavity thus filled, said second cavity being opened towards the upper surface and having a substantially concave profile; totally filling this second cavity with a dielectric material of a second type; and leveling the free surface of the trench substantially down to the upper surface level. | 03-07-2013 |
20130288450 | SHALLOW TRENCH FORMING METHOD - A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO | 10-31-2013 |
20140145251 | METHOD FOR FORMING AN INSULATING TRENCH IN A SEMICONDUCTOR SUBSTRATE AND STRUCTURE, ESPECIALLY CMOS IMAGE SENSOR, OBTAINED BY SAID METHOD - A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material. | 05-29-2014 |
20140342524 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon. | 11-20-2014 |