Patent application number | Description | Published |
20090248928 | Integrating non-peripheral component interconnect (PCI) resources into a personal computer system - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 10-01-2009 |
20090249098 | Power management for a system on a chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 10-01-2009 |
20090300245 | Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-03-2009 |
20110078356 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 03-31-2011 |
20110242129 | SYSTEM, METHOD AND APPARATUS FOR AN EDGE-PRESERVING SMOOTH FILTER FOR LOW POWER ARCHITECTURE - Embodiments of an apparatus, system and method are described for an edge-preserving smooth filter for low power architecture. A weighted pixel sum may be determined based on a weight of a central pixel and a weight of one or more neighboring pixels. The weight sum for the central pixel may be set to a power of two. An output of the central pixel may be displayed based on the weight sum and the weighted pixel sum. Other embodiments are described and claimed. | 10-06-2011 |
20110271021 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-03-2011 |
20110320673 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-29-2011 |
20120233366 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 09-13-2012 |
20120239839 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 09-20-2012 |
20130061077 | Power Management For A System On A Chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 03-07-2013 |
20130290756 | Power Management For A System On A Chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 10-31-2013 |
20130297843 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-07-2013 |
20130297846 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-07-2013 |
20140237154 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 08-21-2014 |
20140237155 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 08-21-2014 |
20140365796 | Power Management For A System On A Chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 12-11-2014 |
Patent application number | Description | Published |
20110317034 | IMAGE SIGNAL PROCESSOR MULTIPLEXING - In some embodiments, an electronic device comprises a first camera and a second camera, a first buffer to receive a first set of input frames from the first camera and a second buffer to receive a second set of input frames from the second camera, a single image signal processor coupled to the first buffer and the second buffer to process the first set of input frames from the first frame buffer using one or more processing parameters stored in a first memory to generate a first video stream and to process the second set of input frames from the second frame buffer using one or more processing parameters stored in a second memory register to generate a second video stream, and a memory module to store the first video stream and the second video stream. | 12-29-2011 |
20130002901 | FINE GRAINED POWER GATING OF CAMERA IMAGE PROCESSING - Methods and apparatus relating to fine grained power gating of camera image processing are described. In an embodiment, an Image Signal Processor (ISP) includes a first partition to receive and store image sensor data in a memory during a first time period. The ISP also includes a second partition to process the stored image sensor data during a second time period that follows the first time period. The second partition is entered into a low power consumption state during the first time period. Other embodiments are also disclosed and claimed. | 01-03-2013 |
20130004071 | IMAGE SIGNAL PROCESSOR ARCHITECTURE OPTIMIZED FOR LOW-POWER, PROCESSING FLEXIBILITY, AND USER EXPERIENCE - Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed. | 01-03-2013 |
20140267811 | METHOD, APPARATUS, SYSTEM, AND COMPUTER READABLE MEDIUM FOR IMAGE PROCESSING SOFTWARE MODULE CONFIGURATION - Technologies are provided in embodiments for receiving an indication of an image processing service request, retrieve environmental information indicative of an environmental condition of an apparatus, retrieving operational information indicative of an operating condition of the apparatus, determining image processing software configuration information based, at least in part, on the image processing service, the environmental information, and the operational information, and causing configuration of at least one image processing software module based, at least in part, on the image processing software configuration information. | 09-18-2014 |