Patent application number | Description | Published |
20090177804 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) SWITCH - An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch. | 07-09-2009 |
20090177805 | DUAL PORT SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) DISK DRIVE - An embodiment of the present invention is disclosed to include a hard disk drive allowing for access by two hosts to a device. Further disclosed are embodiments for reducing the delay and complexity of the SATA disk drive. | 07-09-2009 |
20090177815 | SWITCHING SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) TO A PARALLEL INTERFACE - An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch. | 07-09-2009 |
20090177831 | ROUTE AWARE SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) SWITCH - An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch. | 07-09-2009 |
20100199134 | DETERMINING SECTOR STATUS IN A MEMORY DEVICE - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased. | 08-05-2010 |
20100211834 | DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface. | 08-19-2010 |
20100228928 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 09-09-2010 |
20100228940 | MEMORY BLOCK MANAGEMENT - Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective. | 09-09-2010 |
20100262721 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-14-2010 |
20120011335 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 01-12-2012 |
20120110244 | COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device. | 05-03-2012 |
20120124304 | MEMORY BLOCK MANAGEMENT - One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block. | 05-17-2012 |
20120182795 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 07-19-2012 |
20120303931 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 11-29-2012 |
20120324180 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 12-20-2012 |
20130007544 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-03-2013 |
20130013978 | DETERMINING SECTOR STATUS IN A MEMORY DEVICE - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased. | 01-10-2013 |
20130073790 | MAGNETIC RANDOM ACCESS MEMORY WITH BURST ACCESS - A memory device which includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable write of the data units of the burst of data, the memory device allowing a next burst write or read command to begin before the completion of the burst write operation and while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130073791 | MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE - A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130073926 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 03-21-2013 |
20130080687 | SOLID STATE DISK EMPLOYING FLASH AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A central processing unit (CPU) subsystem is disclosed to include a MRAM used among other things for storing tables used for flash block management. In one embodiment all flash management tables are in MRAM and in an alternate embodiment tables are maintained in DRAM and are near periodically saved in flash and the parts of the tables that are updated since last save are additionally maintained in MRAM. | 03-28-2013 |
20130250667 | METHOD OF READING FROM AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of writing to a magnetic memory cell that includes selecting a magnetic memory cell having a pair of MTJs, and based on whether the selected magnetic memory cell is an ‘odd’ magnetic memory cell or an ‘even’ magnetic memory cell and a state to which the selected magnetic memory cell is being written, setting a distinct bit line (BL), coupled to a first MTJ of the pair of MTJs or a second MTJ of the pair of MTJs, to a voltage level indicative of a certain state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the first or second MTJs to be in a direction opposite to that of the other one of the first or second MTJs to program the first and second MTJs in opposite states. | 09-26-2013 |
20130268701 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-10-2013 |
20130283124 | DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface. | 10-24-2013 |
20130339587 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible. | 12-19-2013 |
20140047161 | System Employing MRAM and Physically Addressed Solid State Disk - A computer system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047164 | Physically Addressed Solid State Disk Employing Magnetic Random Access Memory (MRAM) - A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption. | 02-13-2014 |
20140047165 | Storage System Employing MRAM and Physically Addressed Solid State Disk - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047166 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140082372 | SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-20-2014 |
20140082374 | MOBILE DEVICE USING SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A mobile device includes an application processor, an RF modem for connection to cellular networks, wireless device for connection to wireless networks, a display coupled to the application processor, audio devices coupled to the application processor, power management for providing power through a main battery; and charging the battery, a hybrid memory including a magnetic memory, the magnetic memory further including a parameter area configured to store parameters used to authenticate access to certain areas of the main memory, and a parameter memory that maintains a first area, used to store protected zone parameters, and a second area used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with access to the certain areas in the main memory that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-20-2014 |
20140143481 | MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. | 05-22-2014 |
20140143489 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 05-22-2014 |
20140201432 | PERSISTENT BLOCK STORAGE ATTACHED TO MEMORY BUS - A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS. | 07-17-2014 |
20140269041 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 09-18-2014 |
20140281069 | MULTI ROOT SHARED PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) END POINT - A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table. | 09-18-2014 |
20140281142 | Storage System Employing MRAM and Redundant Array of Solid State Disk - A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided. | 09-18-2014 |
20140281680 | DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCY - A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components. | 09-18-2014 |
20140281825 | Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell NAND Flash Memory - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 09-18-2014 |
20140289587 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 09-25-2014 |
20140310431 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-16-2014 |
20150019804 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-15-2015 |
20150032943 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 01-29-2015 |
20150032947 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) IN A MOBILE DEVICE - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 01-29-2015 |
20150067449 | FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 03-05-2015 |
20150074347 | SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-12-2015 |
20150089123 | COMPUTER SYSTEM WITH PHYSICALLY-ADDRESSABLE SOLID STATE DISK (SSD) AND A METHOD OF ADDRESSING THE SAME - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 03-26-2015 |