Patent application number | Description | Published |
20100085119 | Generating A Process And Temperature Tracking Bias Voltage - In one embodiment, a method includes generating a current that is proportional to a mobility and an oxide capacitance of a tracking device and independent of a threshold voltage variation of the tracking device, generating a voltage from the current, and providing the voltage as at least part of a bias voltage for another device. In one embodiment, this other device may be a compensation circuit coupled to a main device to compensate for capacitance non-linearity of the main device. | 04-08-2010 |
20110074509 | NON-LINEAR CAPACITANCE COMPENSATION - Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages. | 03-31-2011 |
20130154744 | Non-Linear Capacitance Compensation - Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages. | 06-20-2013 |
Patent application number | Description | Published |
20120306021 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device is provided that includes a first pair of P channel field effect transistors (PFET) with a common source connected to a voltage contact and a gate connected to a drain of the other PFET and a pair of N channel field effect transistors (NFET) sized smaller than the first pair of PFETs with a drain connected to the drain of the respective PFET of the first pair of PFETs, a common source connected to a ground contact, and a gate connected to the drain of an opposite PFET of the first pair of PFETs. Additionally, a second pair of PFETs sized larger than the NFETs and approximately one-half that of the first pair of PFETS, each of the second pair of PFETs having a drain respectively coupled to a connection linking the respective drain of the NFET of the pair of NFETs to the drain of the PFET of the first pair of PFETs. Complementary bit lines are included, each of the complementary bit lines respectively connected to a source of the second pair of PFETs. Finally, a word line connected to a gate of each of the second pair of PFETs. A method for forming the semiconductor device is also disclosed. | 12-06-2012 |
20130224945 | METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS - One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity. | 08-29-2013 |
20130248985 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES WITH A RECESSED CHANNEL - Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening. | 09-26-2013 |
20140070358 | METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR - A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C. | 03-13-2014 |
20140183551 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 07-03-2014 |
20140183638 | METHODS OF USING A TRENCH SALICIDE ROUTING LAYER - Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure. | 07-03-2014 |
20140197411 | METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE - A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess. | 07-17-2014 |
20150053981 | METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE - A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess. | 02-26-2015 |
20150249129 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 09-03-2015 |
20150270346 | SEMICONDUCTOR DEVICES WITH A REPLACEMENT GATE STRUCTURE HAVING A RECESSED CHANNEL - Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening. | 09-24-2015 |
Patent application number | Description | Published |
20080224185 | SEMICONDUCTOR DEVICE HAVING A METAL CARBIDE GATE WITH AN ELECTROPOSITIVE ELEMENT AND A METHOD OF MAKING THE SAME - A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element. | 09-18-2008 |
20080261374 | SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE - A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first mesa and the second mesa. The trench is filled with an isolation material to a height above a top surface of the first conductive layer. The first conductive layer is removed from the second mesa. A second conductive layer is formed over the first separation layer of the first mesa and over the second mesa. A planarizing etch removes the second conductive layer from over the first mesa. A first transistor of a first type is formed in the first mesa, and a second transistor of a second type is formed in the second mesa. | 10-23-2008 |
20090286387 | Modulation of Tantalum-Based Electrode Workfunction - A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer ( | 11-19-2009 |
20130249015 | SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES - An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon. | 09-26-2013 |
Patent application number | Description | Published |
20150037945 | EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE - Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins. | 02-05-2015 |
20150050792 | EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES - Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench. | 02-19-2015 |
20150221770 | EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE - Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins. | 08-06-2015 |
Patent application number | Description | Published |
20150243563 | INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES - In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack. | 08-27-2015 |
20150243652 | INTEGRATION METHOD FOR FABRICATION OF METAL GATE BASED MULTIPLE THRESHOLD VOLTAGE DEVICES AND CIRCUITS - In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage. | 08-27-2015 |
20150243658 | INTEGRATED CIRCUITS WITH VARYING GATE STRUCTURES AND FABRICATION METHODS - Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s). | 08-27-2015 |