Patent application number | Description | Published |
20120068241 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 03-22-2012 |
20120068254 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other. | 03-22-2012 |
20120139030 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer. | 06-07-2012 |
20120273747 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide. | 11-01-2012 |
20130015519 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM Fujii; ShosukeAACI Yokohama-shiAACO JPAAGP Fujii; Shosuke Yokohama-shi JPAANM Sakuma; KiwamuAACI Yokohama-shiAACO JPAAGP Sakuma; Kiwamu Yokohama-shi JPAANM Fujiki; JunAACI Yokohama-shiAACO JPAAGP Fujiki; Jun Yokohama-shi JPAANM Kinoshita; AtsuhiroAACI Kamakura-shiAACO JPAAGP Kinoshita; Atsuhiro Kamakura-shi JP - According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers. | 01-17-2013 |
20130015520 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction. | 01-17-2013 |
20130069134 | MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES - In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region. | 03-21-2013 |
20130134372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers. | 05-30-2013 |
20130134499 | NONVOLATILE PROGRAMMABLE SWITCHES - A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases. | 05-30-2013 |
20130175490 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure. | 07-11-2013 |
20130181184 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures. | 07-18-2013 |
20130200450 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction. | 08-08-2013 |
20130215670 | MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state. | 08-22-2013 |
20130222011 | PROGRAMMABLE LOGIC SWITCH - One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. | 08-29-2013 |
20130299894 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 11-14-2013 |
20130307047 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively. | 11-21-2013 |
20140008715 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other. | 01-09-2014 |
20140273372 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method includes forming a gate insulating layer structure covering first and second stacked layer structures, forming a first conductive layer on the gate insulating layer structure, forming a sacrifice layer on the first conductive layer, patterning the first conductive layer and the sacrifice layer with a line & space pattern, filling an insulating layer in spaces of the line & space pattern, the insulating layer having an etching characteristic different from the sacrifice layer, forming trenches in lines of the line & space pattern by removing the sacrifice layer selectively, the trenches exposing the first conductive layer between the first and second stacked layer structures, and forming a second conductive layer on the first conductive layer in the trenches. | 09-18-2014 |
20150048440 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 02-19-2015 |
20150287913 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures. | 10-08-2015 |
Patent application number | Description | Published |
20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 10-16-2008 |
20090016108 | NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage. | 01-15-2009 |
20090242960 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate electrode provided on the semiconductor substrate via a gate insulation film, and a resistor element provided on the semiconductor substrate and formed of polysilicon. The control gate electrode is entirely formed of a silicide layer. An upper portion of the first gate electrode partially includes a silicide layer. | 10-01-2009 |
20100177546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 07-15-2010 |
20110267867 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 11-03-2011 |
20120135356 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 05-31-2012 |
Patent application number | Description | Published |
20080245553 | INTERCONNECTION, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - An interconnection includes a bundle of conductive members, each of the conductive members being made of carbon nanotube having an end connected to a first conductive film, and another end connected to a second conductive film separated from the first conductive film; and carbon particles each having a diamond crystal structure, dispersed between the conductive members. | 10-09-2008 |
20110050080 | ELECTRON EMISSION ELEMENT - According to the embodiment, an electron emission element includes a conductive substrate, a first diamond layer of a first conductivity type formed on the conductive substrate, and a second diamond layer of the first conductivity type formed on the first diamond layer. Thereby, it becomes possible to provide the electron emission element having a high electron emission amount and a high current density even in a low electric field at low temperature and the electron emission apparatus using this electron emission element. | 03-03-2011 |
20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
20110233779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed. | 09-29-2011 |
20120228614 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate. | 09-13-2012 |
20130217226 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer. | 08-22-2013 |
Patent application number | Description | Published |
20090065476 | METHOD FOR MANUFACTURING LIQUID DISCHARGE HEAD - A method for manufacturing a substrate for a liquid discharge head having a silicon substrate provided with a supply port of a liquid comprises steps of preparing a substrate which is provided with a passive film on one side face thereof, has a first recess and a second recess provided therein so as to penetrate from the one side face into the inner part through the passive film, wherein the recesses satisfy a relation of a×tan 54.7 degrees≦d, when a is defined as a distance between the first recess and the second recess, and d is defined as a depth of the second recess, and forming the supply port by anisotropically etching the crystal from the one side face. | 03-12-2009 |
20090315953 | LIQUID EJECTION HEAD AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a liquid ejection head having an element which generates energy utilized for ejecting liquid and an electrode layer electrically connected the element. The method includes the steps of: providing an electrode layer on a substrate, a width of one portion of the electrode layer being smaller than that of another portion near the one portion; providing a resist layer on a part of the electrode layer by any one of a screen printing method and a dispense method in such a manner that an end of the resist layer is positioned at the one portion; providing another layer on another part excluding the part of the electrode layer by utilizing the resist layer as a mask; and removing the resist layer. | 12-24-2009 |
20090315955 | LIQUID EJECTION HEAD - It is an objective of the present invention to provide an ink jet printing head substrate by which a high adhesion can be obtained between an electrode layer and a nozzle formation member and the corrosion or electrolysis for example of a electrode due to the contact between the electrode and ink can be reduced. To realize this, the present invention includes: an electrode layer for supplying power to a heat-generating portion that is provided on a substrate and that generates thermal energy for ejecting ink; and a resin layer provided on the electrode layer via a nickel-containing layer. The electrode layer includes precious metal as a main component. The nickel-containing layer consists of gold-nickel alloy containing nickel. | 12-24-2009 |
20090315958 | LIQUID EJECTION HEAD - Provided is a liquid ejection head having a structure in which an organic resinous member is formed in contact with a substrate. The substrate includes heat generators for generating heat energy used to eject ink, when being energized, and a metallic line portion for energizing the heat generators. The organic resinous member is provided with ejection openings corresponding to the heat generators. In the liquid ejection head, the substrate and the organic resinous member have an improved adhesion therebetween, and are prevented from being separated from each other. To improve the adhesion, the metallic line portion is cut so that no line portion exists under an end part of the organic resinous member (nozzle formation member). Then, two members of the line portion thus cut are connected to each other through a roundabout line formed under an insulating layer which has a good adhesion to the organic resin. | 12-24-2009 |
20140013600 | MANUFACTURING METHOD OF SUBSTRATE FOR LIQUID EJECTION HEAD - Provided is a method for manufacturing a substrate for liquid ejection head including an ejection energy generating element and a nozzle layer including an ejection port and a liquid channel. The method includes the steps of: forming, on the substrate including the element, a metal mold member made of metal and having a flat surface, the metal mold member making up at least a part of a mold for the liquid channel, and a planarization layer made of the metal and having a flat surface to planarize a surface of the nozzle layer; coating the mold for the liquid channel and the planarization layer with negative-type photosensitive resin, thus forming a negative-type photosensitive resin layer to be the nozzle layer; exposing the resin layer to ultraviolet rays, thus forming the ejection port; and selectively removing the mold for the liquid channel, thus forming the liquid channel. | 01-16-2014 |
20140030427 | METHOD OF MANUFACTURING LIQUID EJECTION HEAD - A method of manufacturing a liquid ejection head includes forming, on the substrate, a metal layer formed of a first metal, forming a liquid flow path pattern formed of a second metal that is a metal of a different kind from that of the first metal and that is dissolvable in a solution that does not dissolve the first metal, the liquid flow path pattern being formed on at least a part of a surface of the metal layer, covering the metal layer and the pattern with an inorganic material layer to be formed as the nozzle layer, forming the ejection orifices in the inorganic material layer, and removing the pattern by the solution. A standard electrode potential E | 01-30-2014 |
20140218439 | LIQUID DISCHARGE DEVICE AND CLEANING METHOD FOR LIQUID DISCHARGE HEAD - A liquid discharge device includes a liquid discharge head including a discharge port surface on which discharge ports for discharging liquid are formed, an electrothermal conversion element configured to generate energy for discharging liquid from the discharge ports, and a protection film configured to cover at least the electrothermal conversion element, and a cap configured to cover the discharge port surface, wherein the cap is arranged along the discharge port surface at a position opposite to the protection film via the discharge ports in a state where the cap covers the discharge port surface, and wherein the cap includes an electrode configured to be used to apply voltage between the protection film and the electrode. | 08-07-2014 |
20140318976 | REPRODUCTION METHOD OF LIQUID EJECTING HEAD - A reproduction method of a liquid ejecting head including: a process of filling the flow path with an electrolyte solution containing metal, and filling a space between an electrode capable of applying a voltage to between itself and the upper protective film and the upper protective film with the electrolyte solution; and a process of applying a voltage to between the upper protective film and the electrode to make the metal contained in the electrolyte solution deposit on the surface of the upper protective film. | 10-30-2014 |