Patent application number | Description | Published |
20120274265 | ELECTRICAL CHARGE RELAY ENHANCER AND SOLAR CELL SYSTEM INCLUDING THE ENHANCER - A charge relay enhancer used in relaying a charge produced in a solar cell to a charger, and a solar cell system including the charge relay enhancer. The charge relay enhancer includes: a charge induction and pumping device inducing a charge by using a power voltage from among two power voltages of different polarities selected in response to a control signal, and pumping the induced charge; and a charge pathway selecting device relaying the charge input to an input terminal via two input/output terminals, to the charge induction and pumping device, receiving the charge pumped by the charge induction and pumping device via the two input/output terminals, and outputting the charge to an output terminal. Accordingly, as charges produced in a solar cell may be relayed to a charging device as much as possible, efficiency of relaying charges produced in the solar cell to the charging device may be maximized. | 11-01-2012 |
20140051783 | ECO-FRIENDLY RESIN COMPOSITION - Disclosed is an eco-friendly resin composition. The eco-friendly resin composition includes a base resin of about 100 parts by weight and a polyvinylacetal compatibilizer of about 1 to about 20 parts by weight. The base resin includes a plasticized cellulose diacetate of about 10 wt % to about 50 wt % and a thermoplastic resin of about 50 wt % to about 90 wt %. | 02-20-2014 |
20140135440 | POLYPROPYLENE RESIN COMPOSITION FOR INTERIOR MATERIALS OF AUTOMOBILE WITH ADVANCED PAINT ADHESIVITY AND LOW SPECIFIC GRAVITY - Disclosed is a polypropylene resin composition for automobile interior trim parts with superior paint adhesivity and low specific gravity. More specifically, a polypropylene resin composition for automobile interior trim parts having superior paint adhesivity and low specific gravity is disclosed, wherein a base resin including polypropylene, a propylene-ethylene copolymer or a mixture thereof is mixed with a reinforcer including magnesium hydroxide and an ethylene-butene elastomer. The present polypropylene resin composition allows for direct painting of an automobile interior trim part surface without primer treatment and provides excellent resistance to damage caused by impact. | 05-15-2014 |
20140187694 | POLYPROPYLENE RESIN COMPOSITION AND INTERIOR AND EXTERIOR MATERIALS FOR VEHICLES USING THE SAME - Disclosed is a polypropylene resin composition and interior and exterior materials for vehicles using the same, particularly an olefin-based polypropylene resin composition including: about 50 to 70% by weight of a high crystalline polypropylene; about 10 to 20% by weight of a reactor made thermoplastic polyolefin (RTPO) polypropylene; about 5 to 20% by weight of an inorganic filler; about 10 to 20% by weight of a rubber elastomer; and about 3% by weight or less of a slip agent, based on the total weight of the composition. The composition provides excellent physical properties such as high strength and impact resistance, and thus superior resistance to damage, and shows low gloss characteristics and excellent fluidity. | 07-03-2014 |
20140206806 | POLYOLEFIN-BASED RESIN COMPOSITION - Disclosed are a polyolefin-based resin composition having excellent scratch resistance and low glossiness, a preparation method thereof, and automobile interior and exterior materials fabricated therefrom. The polyolefin-based resin composition comprises about 56 to 97% by weight of a polypropylene block copolymer resin, about 1 to 9% by weight of a thermoplastic elastomer rubber, about 1 to 30% by weight of an inorganic filler, and about 1 to 5% by weight of a fluoroacrylamide-based copolymer based on a total weight of the composition. | 07-24-2014 |
20150073076 | POLYPROPYLENE RESIN COMPOSITION HAVING IMPROVED MECHANICAL PROPERTIES - Disclosed is a polypropylene resin composition having superior mechanical properties. More particularly, the polypropylene resin composition includes glass fiber and talc as fillers under an optimized condition and includes an ethylene-butene elastomer. The polypropylene resin composition exhibits no cracking, even when exposed to aromatic compounds or various chemicals, because of its superior chemical resistance, is easily processable because of its excellent mechanical properties such as impact strength, rigidity, etc., and is useful for use in automotive interior parts because of its superior scratch resistance, molding shrinkage, etc. | 03-12-2015 |
20150175790 | POLYPROPYLENE RESIN COMPOSITION - The present invention provides a polypropylene resin composition including (A) about 60 to 80% by weight of a base resin selected from the group consisting of a high crystalline polypropylene, a propylene-ethylene copolymer, and a mixture thereof; (B) about 2 to 8% by weight of a styrene-ethylene/butene-styrene elastomer; (C) about 6 to 10% by weight of an ethylene-octene elastomer; (D) about 5 to 10% by weight of whisker; (E) about 2 to 8% by weight of talc; (F) about 1 to 3% by weight of a modified polypropylene grafted with maleic anhydride; (G) about 1 to 5% by weight of a vinyl-based acetal compatibilizer; and (H) about 1 to 3% by weight of a slipping agent containing a siloxane-based compound and an amide-based compound, with respect to the total weight of polypropylene. Polypropylene resin compositions according to the present invention can exhibit excellent physical properties such as high stiffness and impact resistance even though formed into a thin film. Hence, the polypropylene resin composition of the present invention can be effectively applied as a vehicle interior material such as a door trim, a pillar trim, a tail gate, and further can contribute to reducing weight of a vehicle. | 06-25-2015 |
20160002436 | POLYPROPYLENE-BASED RESIN COMPOSITION AND METHOD FOR MANUFACTURING POLYPROPYLENE COMPOSITE MATERIAL - The present invention relates to a polypropylene-based resin composition including: (A) a polypropylene resin in an amount of about 40 to 90 wt %, (B) a metal hydroxide in an amount of about 1 to about 25 wt %, (C) an inorganic filler in an amount of about 5 to about 15 wt %, and (D) a polyolefin-based elastomer in an amount of about 0 to about 20 wt %, and a method for manufacturing the polypropylene-based resin composition. | 01-07-2016 |
Patent application number | Description | Published |
20090154213 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 06-18-2009 |
20090154265 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 06-18-2009 |
20100259963 | Data line layouts - A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads. | 10-14-2010 |
20110286254 | Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 11-24-2011 |
20110305059 | Semiconductor Memory Devices - Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer. | 12-15-2011 |
20110305100 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers | 12-15-2011 |
20120020142 | RESISTIVE MEMORY - Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current. | 01-26-2012 |
20120063194 | SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME - Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion. | 03-15-2012 |
20120087177 | SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING - A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage. | 04-12-2012 |
20120106281 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS - A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal. | 05-03-2012 |
20120212989 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors. | 08-23-2012 |
20120230139 | SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME - A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell. | 09-13-2012 |
20120260060 | MEMORY DEVICE, COMPUTER SYSTEM INCLUDING THE SAME, AND OPERATING METHODS THEREOF - A memory device includes a hash table storing a hash value, a bit value, and a page address for each of a plurality of pages, a memory cell unit configured to store the pages and output contents corresponding to the page addresses of the pages having a same hash value, and a controller including a comparator configured to compare the contents output from the memory cell unit and change at least one bit value associated with a respective one of the pages upon determining that the contents of the pages are the same. | 10-11-2012 |
20120317352 | Method and Apparatus for Refreshing and Data Scrubbing Memory Device - At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing. | 12-13-2012 |
20130039135 | MEMORY DEVICE FOR MANAGING TIMING PARAMETERS - A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types. | 02-14-2013 |
20130043525 | SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars. | 02-21-2013 |
20130055048 | BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM - A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information. | 02-28-2013 |
20130058145 | MEMORY SYSTEM - A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells. | 03-07-2013 |
20130060985 | DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY - A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit. | 03-07-2013 |
20130170274 | SEMICONDUCTOR MEMORY DEVICE STORING MEMORY CHARACTERISTIC INFORMATION, MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF - A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs. | 07-04-2013 |
20130329478 | Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 12-12-2013 |
20140149652 | MEMORY SYSTEM AND METHOD OF MAPPING ADDRESS USING THE SAME - In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module. | 05-29-2014 |
20140189215 | MEMORY MODULES AND MEMORY SYSTEMS - A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively. | 07-03-2014 |
20140219042 | MEMORY DEVICE AND METHOD OF REFRESHING IN A MEMORY DEVICE - In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed. | 08-07-2014 |
20140237177 | MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME - A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. The slave memory device may be connected to receive the refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. | 08-21-2014 |
20140245105 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES - A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data. | 08-28-2014 |
20140268978 | SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME - A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays. | 09-18-2014 |
20140310481 | MEMORY SYSTEM - A memory system includes a memory controller to control a first memory device and a second memory device. The first and second memory devices are different in terms of at least one of physical distance from the memory controller, a manner of connection to the memory controller, error correction capability, or memory supply voltage. The first and second memory devices also have different latencies. | 10-16-2014 |
20150049570 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF - In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank. | 02-19-2015 |
20150089327 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region. | 03-26-2015 |
20150134895 | SEMICONDUTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block. | 05-14-2015 |
20150155055 | TEST METHOD OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area. | 06-04-2015 |
20150199234 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY DEVICE - A method of operating a memory device includes: checking for errors in data read from a first address of a memory cell array of the memory device; counting the number of errors that occurred in the data read from the first address; receiving a first command for data read from the first address; determining whether the number of errors that occurred in the data read from the first address is greater than or equal to a first value; and mapping the first address to a second address, if the number of errors that occurred in the data read from the first address is greater than or equal to the first value. | 07-16-2015 |
20150248329 | Method and Apparatus for Refreshing and Data Scrubbing Memory Device - At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing. | 09-03-2015 |
20150309743 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased. | 10-29-2015 |
20160124784 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES - A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data. | 05-05-2016 |