Patent application number | Description | Published |
20100176890 | System and Method for Characterizing Process Variations - A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively. | 07-15-2010 |
20100244853 | Method and Apparatus for Diagnosing an Integrated Circuit - System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determine the location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure. | 09-30-2010 |
20110038451 | ULTRA HIGH RESOLUTION TIMING MEASUREMENT - An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages. | 02-17-2011 |
20110121856 | System and Method for Detecting Soft-Fails - A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs. | 05-26-2011 |
20110273967 | ULTRA HIGH RESOLUTION TIMING MEASUREMENT - A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module. | 11-10-2011 |
20110303984 | Quadrangle MOS Transistors - A quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides of a square. At least two of the four transistor units are connected in parallel. | 12-15-2011 |
20120038388 | RC Delay Detectors with High Sensitivity for Through Substrate Vias - A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units. | 02-16-2012 |
20120112763 | Method for Detecting Small Delay Defects - System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group. | 05-10-2012 |
20120273782 | INTERPOSERS OF 3-DIMENSIONAL INTEGRATED CIRCUIT PACKAGE SYSTEMS AND METHODS OF DESIGNING THE SAME - An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer. | 11-01-2012 |
20130047049 | BUILT-IN SELF-TEST FOR INTERPOSER - A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit. | 02-21-2013 |
20130127441 | APPARATUS AND METHOD FOR ON-CHIP SAMPLING OF DYNAMIC IR VOLTAGE DROP - Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time. | 05-23-2013 |
20130147505 | TEST PROBING STRUCTURE - A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps. | 06-13-2013 |
20130193981 | SWITCHED CAPACITOR COMPARATOR CIRCUIT - A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal. | 08-01-2013 |
20130257564 | POWER LINE FILTER FOR MULTIDIMENSIONAL INTEGRATED CIRCUITS - An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer. | 10-03-2013 |
20130305112 | Method and Apparatus for Diagnosing an Integrated Circuit - System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determine the location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure. | 11-14-2013 |
20140075404 | GROUP BOUNDING BOX REGION-CONSTRAINED PLACEMENT FOR INTEGRATED CIRCUIT DESIGN - Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit. | 03-13-2014 |
20140082575 | METHOD FOR PLACING DECOUPLING CAPACITORS - A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold and inserting a plurality of decoupling capacitors adjacent to the hot spots. | 03-20-2014 |
20140239427 | Integrated Antenna on Interposer Substrate - Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane. | 08-28-2014 |
20140282305 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 09-18-2014 |
20150095869 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND A CONTROL SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold. | 04-02-2015 |
20150113493 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING LAYOUT FOR SEMICONDUCTOR DEVICE - A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment. | 04-23-2015 |
20150161318 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold. | 06-11-2015 |
20150213178 | TIER BASED LAYER PROMOTION AND DEMOTION - Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified. | 07-30-2015 |
20150213182 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 07-30-2015 |
20150331990 | SEMICONDUCTOR ARRANGEMENT FORMATION - A method of forming a semiconductor arrangement is provided. The semiconductor arrangement includes an interconnection arrangement comprising a first connection between a driver and a receiver. At least one buffer is disposed along the first connection to reduce delay associated with the interconnection arrangement. However, buffers increase power consumption, and thus a determination is made as to whether a buffer is unnecessary. A buffer is determined to be unnecessary where removal of the buffer does not violate a timing constraint regarding an amount of time a signal takes to go from the driver to the receiver. If a buffer is determined to be unnecessary, the buffer is removed to reduce power consumption. | 11-19-2015 |
Patent application number | Description | Published |
20130128567 | Light Emitting Diode (LED) Lamp Tube Structure - An improved light emitting diode (LED) lamp tube structure, comprising a lampshade, at least an LED lamp strap installed inside the lampshade and at least a drive circuit installed on any side of the interior of the lampshade, wherein the drive circuit includes multiple electronic components and a drive circuit board, in which the electronic components are insertion installed on one side of the drive circuit board, and at least an LED is insertion installed on the other side of the drive circuit board. Therefore, when the drive circuit drives the LED lamp strap to illuminate, it also drives the LEDs insertion installed on the other side of the drive circuit board to light up at the same time so the entire lampshade can illuminate completely. | 05-23-2013 |
20130155669 | Separate Drive Circuit Structure for LED Lamp Tube - A separate drive circuit structure for light emitting diode (LED) lamp tube, wherein the LED lamp tube comprises a lampshade and at least an LED lamp strap installed inside the lampshade, and the left and right sides of the LED lamp strap in the interior of the lampshade are respectively installed with a separate drive circuit structure. The separate drive circuit structures disposed at the two ends are connected with a transmission line such that the separate drive circuit structures disposed at the two ends together constitute a drive circuit capable of driving the LED lamp strap to illuminate. Moreover, the separate drive circuit structure can effectively reduce the tube diameter of the lampshade. | 06-20-2013 |
20130215609 | Lamp Tube Connector Structure for Light Emitting Diode (LED) Lamp Tube - An improved lamp tube connector structure for light emitting diode (LED) lamp tube, in which the LED lamp tube comprises a lampshade, two lamp tube connectors installed on the left and right ends of the lampshade, at least an LED lamp strap installed inside the lampshade, and at least a drive circuit board installed inside the lamp tube connector and electrically connected to either side of the LED lamp strap. Herein the lamp tube connector is an end cap, with two electrode terminals extending outward from the end cap. Also, at least two connection lines extend from the drive circuit board, and the drive circuit board is inserted to the interior of the electrode terminal so as to form an electrically conductive contact with the electrode terminal for transferring electric power. | 08-22-2013 |
20130223053 | Drive Circuit Board Connection Structure for LED Lamp Tube - An improved drive circuit board connection structure for light emitting diode (LED) lamp tube, wherein the LED lamp tube comprises a lamp tube body, at least an LED lamp strap installed inside the lamp tube body, and at least a drive circuit board installed on either side of the lamp tube body and electrically connected to the LED lamp strap. A connection plug component is respectively installed on the drive circuit board and the LED lamp strap, with each of the two different connection plug component individually having a male plug connection structure or female plug connection structure. Therefore, when such two different connection plug components are connected, it is possible to electrically connect the drive circuit board to the LED lamp strap and drive the LED lamp strap to illuminate. | 08-29-2013 |
20130229250 | Magnetic Component Structure - An improved magnetic component structure, wherein the structure comprises a base and two iron cores, in which the base includes a centrally through winding axle tube and the openings at both the left and right ends of the winding axle tube individually extend out a baffle. Additionally, the two iron cores are caps, in which a core column extends out from the center of the iron core toward the opening of the winding axle tube, and the core column can be inserted to the centrally through part of the winding axle tube. Therefore, the two iron cores can be clip installed between the two sets of pin parts of the base and left and right assembled to the base such that the base combined with the two iron cores can be installed upright on one side having the notch of a drive circuit board in an LED light tube. | 09-05-2013 |
Patent application number | Description | Published |
20150121317 | MULTI-PATTERNING SYSTEM AND METHOD - A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state. | 04-30-2015 |
20150143311 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An operation of at least one first circuit element in the first substrate is simulated based on the first environment temperature. | 05-21-2015 |
20150149977 | PARTITIONING METHOD AND SYSTEM FOR 3D IC - A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting. | 05-28-2015 |
20150179568 | Method and Apparatus of a Three Dimensional Integrated Circuit - An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose. | 06-25-2015 |
20150254389 | INTEGRATED CIRCUIT DESIGN SYSTEM WITH COLOR-CODED COMPONENT LOADING ESTIMATE DISPLAY - A method comprises generating a schematic of an integrated circuit (IC), the IC having a circuit component. The method also comprises searching a database having one or more configurations of the circuit component, each of the one or more configurations of the circuit component having a corresponding estimated resistance capacitance (RC) value and an assigned color scheme based on the estimated RC value. The method further comprises displaying the circuit component in the schematic as a symbol representing the circuit component, the symbol representing the circuit component being displayed having the assigned color scheme of a selected circuit component configuration. The method additionally comprises displaying a layout of the IC based on a determination that the schematic passed a design rule check, the displayed layout of the IC including the selected configuration of the circuit component, the selected configuration being displayed in the layout having the assigned color scheme. | 09-10-2015 |
20160070839 | METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC. | 03-10-2016 |