Patent application number | Description | Published |
20100101710 | METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst. | 04-29-2010 |
20110209816 | METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst. | 09-01-2011 |
20120132358 | METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst. | 05-31-2012 |
20120298396 | GRAPHENE FIBER, METHOD FOR MANUFACTURING SAME AND USE THEREOF - The present disclosure relates to a manufacturing method of a graphene fiber, a graphene fiber manufactured by the same method, and use thereof. The graphene fiber formed by using graphenes of linear pattern can be applied to various fields such as an electric wire and coaxial cable. | 11-29-2012 |
20130299077 | METHOD FOR TRANSFERRING GRAPHENE USING A HOT PRESS - The present invention relates to a method for transferring graphene using a hot press, comprising: a step of contacting graphene, having a thermal-releasable sheet attached thereto, with a target substrate; and a step of pressing and heating the graphene having the thermal-releasable sheet attached thereto and the target substrate using the upper press and lower press of a hot press so as to separate the thermal-releasable sheet and the graphene and transfer the separated graphene to the target substrate. The present invention also relates to a graphene-transfer hot press apparatus for said transfer process. | 11-14-2013 |
Patent application number | Description | Published |
20140242354 | ENCAPSULATION FILM WITH THIN LAYER COMPOSED OF GRAPHENE OXIDE AND REDUCED GRAPHENE OXIDE AND METHOD FOR FORMING THE SAME - Provided are an encapsulation film formed by stacking at least one bilayer including a thin layer composed of graphene oxide or reduced graphene oxide and an organic polymer layer and a method for forming the same. Since the encapsulation film is formed by stacking at least one bilayer including a thin layer composed of graphene oxide or reduced graphene oxide, the encapsulation film can represent an excellent blocking property with respect to oxygen and moisture. Parallel diffusion of the oxygen and the moisture in the encapsulation film may be significantly limited by maximizing a thickness of the organic polymer layer formed between the thin layers. | 08-28-2014 |
20150060869 | SUPPORTING SUBSTRATE FOR MANUFACTURING FLEXIBLE INFORMAITON DISPLAY DEVICE USING TEMPORARY BONDING/DEBONDING LAYER, MANUFACTURING METHOD THEREOF, AND FLEXIBLE INFORMATION DISPLAY DEVICE - Disclosed are a supporting substrate for manufacturing a flexible information display device using a temporary bonding/debonding layer, a manufacturing method thereof, and a flexible information display device. A supporting substrate for manufacturing a flexible information display device, the supporting substrate comprising: a temporary bonding/debonding layer having a thickness in a range of 0.1 nm to 1000 nm and comprising an adhesive material bonded to the supporting substrate through Van der Waals bonding force. Provided is a method capable of economically manufacturing the display device having a high resolution while reviewing a cost competitive force by reducing a device investment cost and improving the yield rate in the flexible flat panel information display device. | 03-05-2015 |
20150060870 | SUPPORTING SUBSTRATE FOR MANUFACTURING FLEXIBLE INFORMATION DISPLAY DEVICE, MANUFACTURING METHOD THEREOF, AND FLEXIBLE INFORMATION DISPLAY DEVICE - Disclosed are a supporting substrate for manufacturing a flexible information display device capable of easily separating the flexible information display device from the supporting substrate without deforming or damaging the flexible information display device, a manufacturing method thereof, and a flexible information display device manufactured thereby. The supporting substrate for manufacturing a flexible information display device includes: a coating layer formed therein with a plurality micro-protrusions formed on the supporting substrate; and a temporary bonding/debonding layer formed on the coating layer and including an adhesive material mechanically interlocked with and bonded to the supporting substrate through Van der Waals bonding force. The method provides a method capable of economically manufacturing the display device having a high resolution while reviewing a cost competitive force by reducing a device investment cost and improving the yield rate in the flexible flat panel information display device. | 03-05-2015 |
Patent application number | Description | Published |
20080209231 | Contents Encryption Method, System and Method for Providing Contents Through Network Using the Encryption Method - Disclosed are a contents encryption method, and a system and method for providing contents through a network using the contents encryption method. In order to provide contents through the network more securely, at least one piece of contents and corresponding metadata are recursively multi-encrypted at least once, and encrypted data are then provided. In particular, encrypted positions of the contents and corresponding decryption information are expressed as metadata, and the metadata include parameter information on respective encryption tools used for multi-encryption, an order of the applied encryption tools, positions of the encryption tools, and a list of encryption tool substitutes. The metadata are provided when the contents are provided. Therefore, the contents provider and receiver can more safely and systematically manage the metadata including contents decryption information, and multimedia are efficiently protected, managed, and controlled. | 08-28-2008 |
20100014666 | Method and Apparatus for Protecting Scalable Video Coding Contents - Disclosed are a method and apparatus capable of reducing the computational complexity of encryption and decryption by encrypting only data of scalable video coding contents for each coding layer in terms of temporal, spatial, and SNR scalabilities to provide a service for protected scalable video coding contents, and capable of protecting contents by generating and distributing an encryption key for encryption and decryption depending on a class of a contents consumer. | 01-21-2010 |
Patent application number | Description | Published |
20110058441 | DATA LINE DRIVING CIRCUIT - A data line driving circuit includes: an operation period signal generation unit configured to generate an operation period signal for determining a write period and a read period in response to a read command or a write command; and a read data line driving unit configured to fix a read data line to a first voltage level in response to the operation period signal, the read data line being dedicated to a read operation. | 03-10-2011 |
20120195140 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal. The semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads. | 08-02-2012 |
20140298147 | DATA TRANSFERRING SYSTEMS, DATA RECEIVERS AND METHODS OF TRANSFERRING DATA USING THE SAME - Data transferring systems are provided. The data transferring system includes a transmitter and a receiver. The transmitter transmit a reference code signal including a reference value of data, a transmission data signal generated by synthesizing data being transmitted and the reference code signal, and an external data masking signal. The receiver receives the transmission data signal to extract an internal code signal and generates an internal data masking signal in response to the internal code signal and the reference code signal. Further, the receiver generates an internal data signal from the transmission data signal in response to the external data masking signal and the internal data masking signal. Related methods are also provided. | 10-02-2014 |
20150049559 | SEMICONDUCTOR DEVICES, SEMICONDUCTOR SYSTEMS INCLUDING THE SAME, AND METHODS OF INPUTTING DATA INTO THE SAME - Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates an input calibration signal during a mode register write operation and receives an output data and an output calibration signal to control a recognition point of a logic level of the output data according to a delay time of the output calibration signal during a read operation. The second semiconductor device stores the input calibration signal therein during the mode register write operation and outputs the output calibration signal and the output data during the read operation. | 02-19-2015 |
20150139364 | METHOD FOR DETECTING PHASE AND PHASE DETECTING SYSTEM - A phase detection method includes providing by a controller a second control signal having two or more neighboring pulses when the time during which a state of a second control signal is retained is a predetermined time or more, receiving by the controller phase detection results of a phase of a first control signal different from the second control signal in response to the second control signal, and determining by the controller a phase detection result based on a first pulse of the two neighboring pulses of the second control signal, of the phase detection results. | 05-21-2015 |
20150213861 | SEMICONDUCTOR DEVICES - The semiconductor device includes a first data aligner, an input strobe signal generator and a second data aligner. The first data aligner aligns input data in synchronization with an internal strobe signal to generate alignment data. The input strobe signal generator generates first and second delay signals from the internal strobe signal. The input strobe signal generator also latches an input clock signal generated from an external clock signal after a write latency period from a period when a write operation commences, in response to the first and second delay signals to generate an input strobe signal. The second data aligner re-aligns the alignment data in synchronization with the input strobe signal to generate internal data. | 07-30-2015 |
Patent application number | Description | Published |
20110291762 | INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation. | 12-01-2011 |
20130207736 | RESISTANCE MEASURING CIRCUIT, RESISTANCE MEASURING METHOD, AND IMPEDANCE CONTROL CIRCUIT - A resistance measuring method includes: measuring a resistance value of a first path which is formed from an interface pad through a resistor unit to a ground node; measuring a resistance value of a second path which is formed from the interface pad to the ground node but does not pass through the resistor unit; and calculating a resistance value of the resistor unit by subtracting the resistance value of the second path from the resistance value of the first path. | 08-15-2013 |
20140244947 | MEMORY, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF MEMORY CONTROLLER - A memory system includes a memory including a condition detection circuit configured to detect a memory condition, and a condition output circuit configured to output the memory condition detected by the condition detection circuit. A memory controller is configured to adjust operational performance of the memory in response to the memory condition. | 08-28-2014 |
Patent application number | Description | Published |
20140111256 | DESERIALIZERS - Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal. | 04-24-2014 |
20140340247 | DESERIALIZERS - Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal. | 11-20-2014 |
20140344611 | DESERIALIZERS - Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal. | 11-20-2014 |
20140369453 | RECEIVERS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data. | 12-18-2014 |
20150049854 | SHIFT REGISTERS - Shift registers are provided. The shift register includes a first clock buffer and a second clock buffer. The first clock buffer inverts an input signal and a complementary input signal in response to a clock signal to generate a first output signal and a first complementary output signal. The second clock buffer inverts the first output signal and the first complementary output signal in response to the clock signal to generate a second output signal and a second complementary output signal. | 02-19-2015 |
20150235683 | SEMICONDUCTOR DEVICES - A semiconductor device including a data aligner that aligns input data in response to internal strobe signals obtained by dividing a data strobe signal to generate a first alignment data and a second alignment data. The semiconductor device may also include a phase sensor that generates a control clock signal in response to a clock signal and senses phases of the internal strobe signals with the control clock signal to generate a selection signal, and a data selector that selectively outputs the first and second alignment data as a first selection alignment data and a second selection alignment data in response to the selection signal. | 08-20-2015 |
20150357003 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 12-10-2015 |
20150357004 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 12-10-2015 |
20150364163 | INTEGRATED CIRCUITS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A integrated circuit may include an input buffer suitable for buffering a strobe signal in response to a buffer enablement signal to generate an internal strobe signal, an internal clock generator suitable for receiving the internal strobe signal to generate internal clock signals including different phases. The integrated circuit may include a strobe signal driver suitable for driving the strobe signal in response to a drive control signal. The drive control signal may be enabled prior to the buffer enablement signal being enabled. | 12-17-2015 |
20160027478 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 01-28-2016 |
20160080139 | RECEIVERS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data. | 03-17-2016 |
Patent application number | Description | Published |
20090248501 | Calculation method of sales allowance and computer readable recording medium thereof - Disclosed are calculation method of sales allowance and computer readable recording medium thereof that are capable of calculating allowance to be paid to respective members corresponding to each node online in a commodity or service sales method. The method comprises the steps of computing a rate of a ranking of a predetermined subscriber to the number of subscribers included on one line; computing a rate of sales of the predetermined subscriber to the total of sales of respective subscribers included on the one line; computing the rate computed in the step times the rate computed in the step times a sales allowance payment rate of new sales; automatically computing an allowance of the predetermined subscriber by the product of the value computed in the step and a predetermined invariable; and displaying the value computed in the step on the monitor of a computer. Thus, according to the present, it is possible to compute a sales allowance paid to subscribers according to respective steps simply and correctively without manager's complicated computation in case of the generation of new sales by online automatically computing allowances correctively allotted to members included on one line according to a payment rate in a commodity or service sales method. | 10-01-2009 |
20100185528 | METHOD FOR ELECTRONIC COMMERCE USING POINTS, SYSTEM AND RECORDING MEDIUM THEREOF - Embodiments of the present invention relate to a method for electronic commerce, a system, and a recording medium thereof, and more particularly, to a method for electronic commerce using a point on the basis of the grade of a member depending on the position and code of each of a GM member and an SM member on-line, an electronic commerce system, and a recording medium readable by a computer. A method for electronic commerce, an electronic commerce system, and a computer-readable recording medium of embodiments of the present invention have advantages of creating an increase in the number of members having loyalty by enhancing an association relationship between members and providing a higher incentive to a member inducing membership joining and the resultant activation of an on-line enterprise. | 07-22-2010 |
20100205051 | CALCULATION METHOD OF SALES COMMISSION USING TRANSFORMATION COEFFICIENT IN ON-LINE, CALCULATION SYSTEM AND RECORDING MEDIUM THEREOF - Disclosed are a method and a system of calculating a sales commission using a transformation coefficient in on-line by reflecting sales of members receiving sales commissions and new sales of sub-members, and a record medium thereof. Members receive sales commissions based on members' own sales, so that old sub-members as well as new members actively sell commodities. The property of the tree to which the members belong is more increased, so that the members have reliability and affection for a company. The revenue of the members is more increased, and a company attempts to increase sales and members. A company determines sales commissions paid to members at a constant commission payment rate for the sales of the members without being affected by the enlargement of an organization due to the increase of the members and the amount of sales. | 08-12-2010 |
20110193313 | FOLDABLE BICYCLE - Disclosed is a foldable bicycle. The foldable bicycle includes a head frame having a first connection part, a first lower frame integrally formed with the head frame and provided at a terminal end thereof with a second fastening part, a second lower frame provided with a second connection part extending from one side of the perforation hole, a slide member coupled with the second lower frame to slidably move lengthwise along the second lower frame and provided at an upper portion thereof with a third connection part, a saddle frame provided at a lower portion thereof with a third fastening part rotatably coupled with the third connection part, and a horizontal frame provided at one end thereof with a fourth fastening part rotatably coupled with saddle frame, and at the other end thereof with a first fastening part rotatably coupled with a first connection part. | 08-11-2011 |
20110218901 | ON-LINE PRODUCT AUCTION METHOD USING STOCK INDEX AND RECORDING MEDIUM - An online product auction method using stock price indexes is disclosed. A plurality of bidders participates in online auction bidding for a presented product and inputs respective bid numbers. Specific numbers are extracted from two or more indexes which indicate stock prices. A successful bid number is created by combining the extracted numbers in a predetermined sequence. It is determined whether a bid number identical to the successful bid number exists among the bid numbers. If one or more bid numbers identical to the successful bid number exist, an earliest bidder is selected for a successful bidder. If no bid number identical to the successful bid number exists, an earliest bidder, having a bid number which is the closest to the successful bid number, is selected for a successful bidder. Thereafter, a command is output to deliver the corresponding product to the selected bidder. | 09-08-2011 |
Patent application number | Description | Published |
20100232196 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE PROVIDING ACTIVE TERMINATION CONTROL - A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated. | 09-16-2010 |
20110126066 | MULTI-CHIP MEMORY SYSTEM AND RELATED DATA TRANSFER METHOD - A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus. | 05-26-2011 |
20120030414 | NON VOLATILE MEMORY APPARATUS, DATA CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory. | 02-02-2012 |
20150248250 | METHOD OF OPERATING DATA STORAGE DEVICE - A method of operating a data storage device includes: receiving a single wipe device initialization command from a host, and in response to the wipe device initialization command, executing a wipe device initialization operation that during a single time period initializes the entirety of a mapping table defining logical partitions dividing memory space provided by a physical region of the data storage device. | 09-03-2015 |
Patent application number | Description | Published |
20100026173 | METHOD OF DEPOSITING LIGHT EMITTING LAYER OF ORGANIC EL DEVICE, METHOD OF MANUFACTURING ORGANIC EL DEVICE, AND ORGANIC EL DEVICE MANUFACTURED BY THE METHOD - A method of depositing a light emitting layer of an organic EL device in which a subpixel combination having a plurality of different colors is set as a unit pixel, a plurality of subpixels are sequentially and alternately arranged in a row direction, and a plurality of subpixels of the same color are arranged in a column direction, includes first depositing the light emitting layer using a mask having a plurality of opening portions corresponding to positions of the subpixels of the same color arranged in any of an odd numbered row and an even-numbered column of the subpixels, and second depositing the light emitting layer by moving the mask to prevent the light emitting layer from being deposited at a subpixel adjacent to the subpixel where the light emitting layer is deposited during the first deposition operation, using the same opening portion of the mask used for the first deposition operation of the light emitting layer. | 02-04-2010 |
20100193779 | BOTTOM GATE THIN FILM TRANSISTOR, FLAT PANEL DISPLAY HAVING THE SAME AND METHOD OF FABRICATING THE SAME - A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes. | 08-05-2010 |
20100310974 | Method of fabricating photo mask for organic light emitting display and photo mask so fabricated - A method of fabricating a photo mask for an organic light emitting display comprises forming a light shielding layer on a transparent substrate, coating the light shielding layer with an electron beam resist, performing exposure on the electron beam resist by a vector scan method in accordance with a specific pattern and using an electron beam having a predetermined accelerating voltage, developing the exposed electron beam resist to form an electron beam resist pattern having the specific pattern, and etching the light shielding layer using the electron beam resister pattern as an etching mask. The specific pattern has a shape corresponding to transistors included in a pixel of an organic light emitting display and elements that constitute a capacitor. | 12-09-2010 |
20110024756 | ORGANIC LIGHT EMITTING DISPLAY - The general inventive concept relates to an organic light emitting display that has the same area where the upper and lower electrodes of a capacitor are overlapped for adjacent pixels, for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different. This thereby prevents the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded. | 02-03-2011 |
20110248953 | Touch screen panel - A touch screen panel includes a transparent substrate, connecting patterns on the transparent substrate, the connecting patterns including a plurality of first connecting patterns arranged in a first direction and a plurality of second connecting patterns arranged in a second direction, sensing cells including a plurality of first sensing cells connected in the first direction by the first connecting patterns and a plurality of second sensing cells connected in the second direction by the second connecting patterns, and conductive dummy patterns between adjacent sensing cells, the conductive dummy patterns and sensing cells being positioned at different height levels relative to the transparent substrate, and the conductive dummy patterns including prominences projected toward the sensing cells and partially overlapping the sensing cells. | 10-13-2011 |
20120062487 | Touch Screen Panel and Display Device Having the Same - A touch screen panel and a display device having the same are capable of improving visibility and suppressing the occurrence of a failure caused by static electricity. In one embodiment, the touch screen panel includes a plurality of first sensing cells arranged along a first direction for each column on a transparent substrate. A first connection pattern electrically connects adjacent first sensing cells to each other. A plurality of second sensing cells are arranged along a second direction for each row while being spaced apart from the first sensing cells. A second connection pattern electrically connects adjacent second sensing cells to each other. In the touch screen panel, the first connection pattern comprises a pair of metal patterns and two pairs of dummy transparent patterns. | 03-15-2012 |
20120075257 | Touch Screen Panel - A touch screen panel includes a transparent substrate. A plurality of first and second sensing cells are formed so as to be connected along first and second directions, respectively. The second sensing cells are disposed between the first sensing cells. A plurality of first and second connection patterns connect the first and second sensing cells to one another along the first and second directions, respectively. A first insulating layer is interposed between the first second connection patterns. In the touch screen panel, each of the first connection patterns includes a main bridge pattern separately patterned in a different layer from the first sensing cells connected by the main bridge pattern to connect adjacent first sensing cells to other along the first direction, and one or more sub-bridge patterns which branch from the main bridge pattern, and which have both ends connected to the main bridge pattern so as to form a detour path. | 03-29-2012 |
20140077692 | FLAT PANEL DISPLAY DEVICE HAVING THIN FILM ENCAPSULATION AND, MANUFACTURING METHOD THEREOF - A flat panel display device and a manufacturing method thereof. In the flat panel display device, a thin film encapsulation structure covering a display unit on a substrate includes an alternating layers stack in which organic layers and inorganic layers are alternately stacked; and an AlOx layer on the alternating layers stack as an outermost thin film layer of the thin film encapsulation structure. According to the above structure, because the protective film is adhered onto the AlOx layer of the thin film encapsulation structure, which has a relatively weak adhesive force, the adhering and releasing processes may be performed smoothly, and thus, the thin film encapsulation structure may be prevented from being damaged in the adhering and releasing processes. | 03-20-2014 |
20140091288 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode (OLED) display includes a display panel including a flexible substrate and a thin film encapsulation (TFE) for covering and protecting an organic light emitting element formed on the flexible substrate, a first protective film arranged on the TFE to be opposite to the TFE, a second protective film arranged on the flexible substrate to be opposite to the flexible substrate, a first adhesive disposed between the TFE and the first protective film, a second adhesive disposed between the flexible substrate and the second protective film, a third protective film arranged on the second protective film to be opposite to the second protective film, and a third adhesive disposed between the second protective film and the third protective film. | 04-03-2014 |
20150221883 | FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A flexible display device includes a flexible substrate doped with a dopant so as to control a work function of the flexible substrate; a display unit formed on the flexible substrate, and including a plurality of pixel circuit layers and a plurality of emission layers; and an encapsulation layer formed to cover the display unit. | 08-06-2015 |
20150364717 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes: a substrate; a display unit disposed on the substrate; a barrier unit disposed between the substrate and the display unit; and a buffer unit disposed between the barrier unit and the display unit, wherein a sum of a thickness of the barrier unit and a thickness of the buffer unit is in the range from 0.9 μm to 3 μm. | 12-17-2015 |
Patent application number | Description | Published |
20090134926 | MULTI-PHASE NEGATIVE DELAY PULSE GENERATOR - A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have a first negative delay property respectively and of which an even number is ring-coupled; and a second delay block including second unit blocks which have a second negative delay property respectively and of which even number is ring-coupled. The number of the first unit block and the number of the second unit block are the same. A plurality of output nodes is formed based on one-to-one sharing between the first unit block and the second unit block having output signals of different level. Each output node outputs a pulse generated by racing the output signals of different level to each other which are provided from the first unit block and the second unit block connected to the each output node. | 05-28-2009 |
20100290302 | FUSE CIRCUIT AND DRIVING METHOD THEREOF - A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node. | 11-18-2010 |
20140003168 | SEMICONDUCTOR INTEGRATED CIRCUIT | 01-02-2014 |
20140167293 | INTEGRATED CIRCUIT WITH BUMP CONNECTION SCHEME - An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to receive a signal for a repair to the differential signals. | 06-19-2014 |
20140328130 | INTEGRATED CIRCUIT WITH BUMP CONNECTION SCHEME - An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to receive a signal for a repair to the differential signals. | 11-06-2014 |