Patent application number | Description | Published |
20100062899 | COMBINED POWER TRANSMISSION, START-UP UNIT AND DRIVE SYSTEM - A force transmission device having a hydrodynamic component, disposed between an input and an output, comprising at least a pump shell and a turbine shell, forming an operating cavity in combination, with an actuatable clutch device for at least partially bridging the hydrodynamic component, comprising a clutch component for at least partially bridging the hydrodynamic component, comprising a first clutch component connected with the input and a second clutch component at least indirectly connected to the output, which can be brought into operative engagement with one another through an actuation device, with a vibration absorber disposed in the force flow at least subsequent to the actuatable clutch device, with a housing coupled with the input or with an element coupled non-rotatably to the input and coupled with the pump shell. | 03-11-2010 |
20100193320 | TORQUE TRANSMISSION DEVICE - A torque transmission device comprising a torque converter disposed in a drive train of a motor vehicle, in particular a hydrodynamic torque converter or a fluid clutch, wherein the converter or the fluid clutch comprises a turbine shell and a pump shell which can be coupled through a pump clutch and at least one pump damper with a converter cover, and comprising at least one converter damper and at least one converter lock up clutch. | 08-05-2010 |
20100200347 | OIL CAVITY FOR PENDULUM ELEMENT (ROLLER) OF A CENTRIFUGAL PENDULUM - A centrifugal pendulum in a torsional vibration damper of a drive train of a motor vehicle with a pendulum flange rotating about a rotation axis and several pendulum masses distributed over the circumference, disposed on the latter in a manner capable of swinging. When the internal combustion engine of the drive train induces massive rotational irregularities resulting from high vibration angles in these arrangements, the pendulum masses can be deflected more strongly relative to the pendulum flange and strike the provided swing motion limits. To prevent hard hits of the pendulum masses on the pendulum flanges, it is proposed to dampen the impact areas by hydraulic means and hence to achieve a soft impact. | 08-12-2010 |
20100236228 | Force transmission device in particular for power transmission between a drive engine and an output - A force transmission device, in particular or power transmission between a drive engine and an output, comprising a damper assembly with at least two dampers, which can be connected in series, and a rotational speed adaptive absorber, wherein the rotational speed adaptive tuned mass damper is disposed between the dampers at least in one force flow direction through the force transmission device. | 09-23-2010 |
20100242466 | Force transmission device with a rotational speed adaptive damper and method for improving the damping properties - The invention relates to a force transmission device for power transmission between an input and an output, comprising at least an input and an output, and a vibration damping device disposed in a cavity that can be filled at least partially with an operating medium, in particular oil, the vibration damping device coupled with a rotational speed adaptive absorber, wherein the rotational speed adaptive absorber is tuned as a function of an oil influence to an effective order q | 09-30-2010 |
20100269497 | HYDRODYNAMIC TORQUE CONVERTER - The invention relates to a hydrodynamic torque converter with an impeller connected on the drive side arranged in housing and a turbine driven by the latter, connected with the driven side of the torque converter, with a turbine damper actively disposed between the turbine and driven side. To improve the vibration damping on the driven side of the torque converter, it is proposed the turbine damper with a first damper part formed out of an input part connected with the turbine and an intermediate flange, limited and rotatable opposite and against the action of at least a first energy accumulator and a second damper part with the intermediate flange and an output part limited and rotatable oppositely and against the action of at least a second energy accumulator, wherein an adaptive-speed vibration absorber is arranged on the intermediate flange. | 10-28-2010 |
20110011692 | DRIVE TRAIN, IN PARTICULAR A HYBRID DRIVE TRAIN - A drive train, in particular, a hybrid drive train with a torque converter, which can be operatively connected with a drive through a clutch. The clutch includes an emergency operation actuation device with at least one emergency operation actuation element, which defines a centrifugal oil cavity which includes oil and which is coupled with the drive. | 01-20-2011 |
20120111684 | TORQUE TRANSMISSION DEVICE - A torque transmission device ( | 05-10-2012 |
Patent application number | Description | Published |
20080233107 | SELECTIVE DELIVERY OF MOLECULES INTO CELLS OR MARKING OF CELLS IN DISEASED TISSUE REGIONS USING ENVIRONMENTALLY SENSITIVE TRANSMEMBRANE PEPTIDE - A polypeptide with a predominantly hydrophobic sequence long enough to span a membrane lipid bilayer as a transmembrane helix (TM) and comprising one or more dissociable groups inserts across a membrane spontaneously in a pH-dependant fashion placing one terminus inside cell. The polypeptide conjugated with various functional moieties delivers and accumulates them at cell membrane with low extracellular pH. The functional moiety conjugated with polypeptide terminus placed inside cell are translocated through the cell membrane in cytosol. The peptide and its variants or non-peptide analogs can be used to deliver therapeutic, prophylactic, diagnostic, imaging, gene regulation, cell regulation, or immunologic agents to or inside of cells in vitro or in vivo in tissue at low extracellular pH. The claimed method provides a new approach for diagnostic and treatment diseases with naturally occurred (or artificially created) low pH extracellular environment such as tumors, infarction, stroke, atherosclerosis, inflammation, infection, or trauma. The method allows to translocate cell impermeable molecules (peptides, toxins, drugs, inhibitors, nucleic acids, peptide nucleic acids, imaging probes) into cells at low pH. The method allows to attach to the cell surface a variety of functional moieties and particles including peptides, polysaccharides, virus, antigens, liposomes and nanoparticles made of any materials. | 09-25-2008 |
Patent application number | Description | Published |
20100252810 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 10-07-2010 |
20110006367 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 01-13-2011 |
20110315950 | NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE - In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions. | 12-29-2011 |
20120038056 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 02-16-2012 |
20120286377 | Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof - Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions. | 11-15-2012 |
20120305886 | NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE - In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions. | 12-06-2012 |
20130087860 | BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS - Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions. | 04-11-2013 |
20130087882 | LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION - Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS). | 04-11-2013 |
20130234260 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 09-12-2013 |
20150118854 | MOLECULAR RADICAL ETCH CHEMISTRY FOR INCREASED THROUGHPUT IN PULSED PLASMA APPLICATIONS - As device feature size shrinks, plasma induced damage is a major concern affecting micro-electronic and nano-electronic device fabrication. Pulsed plasmas are a means of mitigating the damages. However, in conventional standard etch chemistry, the etch rate for pulsed plasmas is reduced significantly resulting in a substantially decreased throughput of tech processes. A new etch chemistry is disclosed in the present invention to increase throughput in pulsed plasma applications driven mainly by the molecular radicals. | 04-30-2015 |
20150151961 | LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION - Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS). | 06-04-2015 |
Patent application number | Description | Published |
20130056874 | Protection of intermetal dielectric layers in multilevel wiring structures - A semiconductor device is accepted at a stage of its fabrication, at which stage the device includes a diffusion-barrier cap-material (DBCM) layer and an intermetal dielectric layer covering the DBCM layer. The DBCM layer is exposed and it is suitable for removal by an etching procedure in a portion of a pattern contained in the intermetal dielectric layer. A silylation treatment is performed on the semiconductor device prior to the etching procedure for removing the DBCM layer. The intermetal dielectric layer of the completed device has surfaces in contact with metal interconnects and metal vias, and it may have an excess of carbon content near at least a portion of the these surfaces. | 03-07-2013 |
20130105916 | HIGH SELECTIVITY NITRIDE ETCH PROCESS | 05-02-2013 |
20130105996 | LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER | 05-02-2013 |
20130108833 | HIGH FIDELITY PATTERNING EMPLOYING A FLUOROHYDROCARBON-CONTAINING POLYMER | 05-02-2013 |
20140048884 | DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES - After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer. A pattern including openings is formed within the photoresist layer. The pattern is subsequently transferred through the hard mask layer and the carbon-based template layer with high selectivity to gate spacers to form self-aligned cavities within the carbon-based template layer. Contact structures are formed within the carbon-based template layer by a damascene method. The hard mask layer and the carbon-based template layer are subsequently removed selective to the contact structures. The contact structures can be formed as contact bar structures or contact via structures. Optionally, a contact-level dielectric layer can be subsequently deposited. | 02-20-2014 |
20140051239 | DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES - After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer. A pattern including openings is formed within the photoresist layer. The pattern is subsequently transferred through the hard mask layer and the carbon-based template layer with high selectivity to gate spacers to form self-aligned cavities within the carbon-based template layer. Contact structures are formed within the carbon-based template layer by a damascene method. The hard mask layer and the carbon-based template layer are subsequently removed selective to the contact structures. The contact structures can be formed as contact bar structures or contact via structures. Optionally, a contact-level dielectric layer can be subsequently deposited. | 02-20-2014 |
20140159227 | PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS - Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. | 06-12-2014 |
20140159242 | PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS - An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. | 06-12-2014 |
20140367833 | Low-Temperature Sidewall Image Transfer Process Using ALD Metals, Metal Oxides and Metal Nitrides - A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate. | 12-18-2014 |
20150118839 | WET CLEAN PROCESS FOR REMOVING CxHyFz ETCH RESIDUE - A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH | 04-30-2015 |
Patent application number | Description | Published |
20120193680 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 08-02-2012 |
20120193715 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 08-02-2012 |
20130026133 | Method to Transfer Lithographic Patterns Into Inorganic Substrates - Techniques for minimizing or eliminating pattern deformation during lithographic pattern transfer to inorganic substrates are provided. In one aspect, a method for pattern transfer into an inorganic substrate is provided. The method includes the following steps. The inorganic substrate is provided. An organic planarizing layer is spin-coated on the inorganic substrate. The organic planarizing layer is baked. A hardmask is deposited onto the organic planarizing layer. A photoresist layer is spin-coated onto the hardmask. The photoresist layer is patterned. The hardmask is etched through the patterned photoresist layer using reactive ion etching (RIE). The organic planarizing layer is etched through the etched hardmask using RIE. A high-temperature anneal is performed in the absence of oxygen. The inorganic substrate is etched through the etched organic planarizing layer using reactive ion etching. | 01-31-2013 |