Patent application number | Description | Published |
20110223350 | METHOD FOR PRODUCING THERMOELECTRIC MATERIAL - A method for producing a thermoelectric material is provided. A semiconductor material powder is provided. An electroless plating process is preformed to deposit metal nano-particles on the surface of semiconductor material powder. An electrical current activated sintering process is performed to form a thermoelectric material having one and plurality grain boundaries. | 09-15-2011 |
20130161559 | HYDROGEN STORAGE COMPOSITES AND METHODS FOR MANUFACTURING THE SAME - Disclosed is a method of forming a hydrogen storage composite, including uniformly covering catalyst particles on the surface of a support to form a hybrid catalyst, and embedding the hybrid catalyst on the surface of a hydrogen storage material to form a hydrogen storage composite. Furthermore, the disclosed also provides a method for manufacturing the same. | 06-27-2013 |
20130164165 | METHODS OF MANUFACTURING MULTI-ELEMENT THERMOELECTRIC ALLOYS - Disclosed is a method of forming a multi-element thermoelectric alloy. A plurality of binary alloys and milling balls are put in a milling pot to perform a ball-milling process to obtain a multi-element thermoelectric alloy powders. The milling balls have a diameter of 1 mm to 10 mm. The milling balls and the binary alloys have a weight ratio of 1:1 to 50:1. The rotation rate of the ball-milling process is of 200 rpm to 1000 rpm. The ball-milling process is processed for 4 hours to 12 hours. | 06-27-2013 |
20140070138 | HYDROGEN STORAGE COMPOSITE MATERIALS AND METHODS OF FORMING THE SAME - A hydrogen storage composite and a method of forming the same are provided. The hydrogen storage composite includes a catalyst mixed with a hydrogen storage base material and a transition metal for catalyzing hydrogen desorption embedded on the surfaces of the hydrogen storage base material and the catalyst. The method includes providing at least one active metal and performing a lengthy time ball mill process to form a catalyst, providing a hydrogen storage base material to mix with the catalyst and performing a lengthy time ball mill process to form a hydrogen storage alloy material, and providing a transition metal for catalyzing hydrogen desorption to mix with the hydrogen storage alloy material and performing a shortened time ball mill process to form a hydrogen storage composite. | 03-13-2014 |
Patent application number | Description | Published |
20100238683 | FLEXIBLE LIGHT-EMITTING APPARATUS - A flexible light-emitting apparatus including a side light-emitting flexible light guide rod, two light emitting diodes, and two lenses is provided. The side light-emitting flexible light guide rod has a first end, a second end opposite to the first end, and a light-emitting surface connecting the first and the second ends. The LEDs are respectively disposed beside the first end and the second end and adapted for emitting light beams toward the side light-emitting flexible light guide rod, respectively. One of the lenses is located between the first end and the LED disposed beside the first end, and the other lens is located between the second end and the LED disposed beside the second end. Each of the light beams enters the side light-emitting flexible light guide rod through the corresponding lens and is transmitted to the outside of the side light-emitting flexible light guide rod through the light-emitting surface. | 09-23-2010 |
20120153339 | LIGHT-EMITTING DIODE CHIP STRUCTURE AND FABRICATION METHOD THEREOF - A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided. | 06-21-2012 |
20120168712 | HIGH BRIGHT LIGHT EMITTING DIODE - A high bright LED comprises a substrate, a conductive layer, a first semiconductor layer, a luminous layer, a second semiconductor layer, a first electrode, a second electrode and an insulation structure. The conductive layer, the first semiconductor layer, the luminous layer and the second semiconductor layer are disposed upwards from an upper solder layer of the substrate in order. The first electrode is electrically connected to the conductive layer The second electrode penetrates through the conductive layer, the first semiconductor layer and the luminous layer to make the upper solder and the second semiconductor layer electrically connected. The insulation structure comprises at least two passivation layers peripherally wrapping the second electrode. The thicknesses of the at least two passivation layers are conformed to the distributed Bragg reflection technique to make the passivation layers jointly used as a reflector with high reflectance. | 07-05-2012 |
20120168768 | SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes: a substrate; one or more semiconductor device layers formed on the substrate; and one or more lattice breaking areas formed on the surface of the substrate between the semiconductor device layers. The invention also provides a method for fabricating a semiconductor structure. | 07-05-2012 |
20130062657 | LIGHT EMITTING DIODE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light-emitting diode structure is disclosed. A substrate has a first semiconductor layer, a light-emitting layer and a second semiconductor layer formed thereon. The first and second semiconductor layers are of opposite conductivity types. A first contact electrode is disposed between the first semiconductor layer and the substrate, and has a protruding portion extending into the second semiconductor layer. A barrier layer is conformally formed on the first contact electrode and exposes a top surface of the protruding portion. A current blocking member is disposed on the barrier layer and around at least a sidewall of the protruding portion. A second contact electrode is disposed between the first semiconductor layer and the first contact electrode, and in direct contact with the first semiconductor layer, wherein the second contact electrode is electrically insulated from the first contact electrode by the barrier layer. | 03-14-2013 |
Patent application number | Description | Published |
20120043679 | METHOD AND DEVICE FOR MAKING AN OPTICAL PLATE FORMED WITH A MICROSTRUCTURE - A method for making an optical plate formed with a microstructure includes: extruding a substrate material and advancing the same to pass through a first nip formed between an embossing roller and a first pressing roller, the embossing roller having a micropatterned surface formed with a plurality of protrusions and a plurality of grooves, the protrusions and the grooves cooperatively defining a microstructure-forming space; applying a photosensitive resin to the micropatterned surface and filling the same into the microstructure-forming space upstream of the first nip to form a plurality of microelements respectively in the microstructure-forming space; allowing the photosensitive resin applied to the micropatterned surface to pass through the first nip together with the substrate material, thereby bonding the microelements to the substrate material; and irradiating and curing the photosensitive resin downstream of the first nip to form the optical plate. | 02-23-2012 |
20120286436 | TWO-SIDED MICROSTRUCTURE FORMING DEVICE AND METHOD FOR FORMING AN OPTICAL PLATE - A microstructure forming device for forming an optical plate includes: a roller unit including a pressing roller, and first and second embossing rollers that respectively have first and second micropatterned surfaces; an extrusion die for extruding a substrate material to a first nip between the first embossing roller and the pressing roller to form a lower microstructure; and a photosensitive resin-applying unit disposed immediately above the second embossing roller for directing a photosensitive resin onto the second embossing roller to form an upper microstructure that is opposite to the lower microstructure. | 11-15-2012 |
20130155722 | LIGHT GUIDE PLATE AND EDGE LIGHT BACKLIGHT DEVICE - An edge light backlight device includes a light guide plate having a base portion and microstructures, LEDs, and a reflective plate. The base portion has a light emitting side, a rear side, and a light incident side. The microstructures are formed on one of the light emitting side and the rear side and each of which extends from the light incident side in a longitudinal direction. Each of the microstructures includes a curved surface with a radius of curvature (R). The light guide plate has a thickness (T). R/T ratio ranges from 0.04 to 0.15 and each of the microstructures has a height ranging from 20 μm to 300 μm so that the light guide plate has a performance of local lighting ranging from 1% to 40%. | 06-20-2013 |
20140185304 | OPTICAL PLATE WITH MICROSTRUCTURES - An optical plate includes a substrate having a light emitting surface, a rear surface opposite to the light emitting surface, and a plurality of microstructures that cooperatively define the light emitting surface and each of which parallelly extends in a light traveling direction. Each of the microstructures includes first and second convex portions and a concave portion disposed between and interconnecting the first and second convex portions, and two adjacent ones of the microstructures are connected. Intersections between the microstructures cooperatively define an imaginary plane, and a lowest point of the concave portion is disposed at one side of the imaginary plane opposite to the rear surface of the substrate. | 07-03-2014 |
20140366346 | Polyester Fiber and Lightweight Woven Nylon Yarn Blended Process - A polyester fiber and lightweight woven nylon yarn blended process may include a lightweight weaving procedure, a secondary lightweight procedure, a dyeing procedure; and a water rinsing and drying procedure. In one embodiment, in the lightweight weaving procedure, a plurality of chemical monofilament fibers is twirled into bunched chemical monofilament fibers by a kneading process, the bunched chemical monofilament fibers and a woven complex yarn (polyester fiber and woven nylon yarn) are fed into a loom simultaneously, the loom is equipped with a fiber opening knife for performing a fiber opening process for the woven complex yarn, the fiber opening knife performs the fiber opening process to cut the woven complex yarn into a plurality of equal sized furcal structures longitudinally to cause wear and tear to achieve lightweight preliminarily, then the furcal structures and the bunched chemical monofilament fibers are undergone a knitting process to obtain a lightweight fabric; | 12-18-2014 |
Patent application number | Description | Published |
20120142862 | RUBBER-MODIFIED POLYSTYRENE RESIN COMPOSITION FOR MAKING AN ELECTROPLATABLE ARTICLE - A rubber-modified polystyrene resin composition is for making an electroplatable article which has a sectioned layer defining a unit area. The rubber-modified polystyrene resin composition includes a resin matrix, occlusion rubber particles dispersed in the resin matrix, and non-occlusion rubber particles dispersed in the resin matrix. A total sectional area ratio of the occlusion rubber particles to the non-occlusion rubber particles in the unit area ranges from 1.1 to 14. | 06-07-2012 |
20130023188 | Apparatus for Wafer Grinding - A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another. | 01-24-2013 |
20130210321 | MODULAR GRINDING APPARATUSES AND METHODS FOR WAFER THINNING - Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer. | 08-15-2013 |
20130220090 | WAFER EDGE TRIM BLADE WITH SLOTS - A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade. | 08-29-2013 |
20140024170 | Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips - A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter. | 01-23-2014 |
Patent application number | Description | Published |
20120056305 | SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width. | 03-08-2012 |
20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
20130034929 | Method for Forming CMOS Image Sensors - A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed. | 02-07-2013 |
20140264506 | METHODS AND APPARATUS FOR CMOS SENSORS - Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end. | 09-18-2014 |
Patent application number | Description | Published |
20090152060 | MAGNETIC RESISTOR CONTROL ASSEMBLY - A magnetic resistor control assembly for a body training machine comprises a main shaft; a rotor, a stator, an adjusting unit, a sliding block set and a controller. An inner disk and an outer disk clamp of the stator clamping the adjusting unit. The sliding block set has guide tracks, an outer lateral wall of each guide track having a track trench. A lower middle portion of the sliding block set has a round hole; the roller being installed and rollable in the guide track; and the retaining rod of the roller is placed within the track trench. A controller is installed at an outer side of the stator; the controller having a transfer pin which displace in the straight grooves. When the transfer pin drives the sliding block set to move in the straight grooves, the gap between permanent magnets and the magnetic isolation ring is changed. | 06-18-2009 |
20100093497 | ATHLETIC APPARATUS WITH NON-LINEAR SLIDING TRACK - An athletic apparatus with non-linear sliding tracks includes a frame, a pair of tracks installed to the frame, a pair of pedal mechanisms slidably installed to the tracks and a pair of rocker arm mechanisms. Each track is formed by at least one curved pipe. Each rocker arm mechanism pivoted to a shaft rod of the frame is linked to the pedal mechanism through at least one linking rod and further connected to a damping mechanism which provides a resistance to the rocker arm mechanism. Each pedal mechanism is linked to a steel rope of a linking mechanism so that the pair of the pedal mechanisms can move back and forth against each other alternately along the curved tracks. A handle is arranged on a top of each rocker arm mechanism, a user can exercise by holding the handles and treading on the pedal mechanism. | 04-15-2010 |
20100151999 | ATHLETIC APPARATUS WITH NON-PARALLEL LINEAR SLIDING TRACK - An athletic apparatus with non-parallel linear sliding tracks includes a frame, a pair of non-parallel linear tracks installed to the frame, a pair of pedal mechanisms slidably installed to the tracks and a pair of rocker arm mechanisms. Each rocker arm mechanism pivoted to a shaft rod of the frame is linked to the pedal mechanism through at least one linking rod and further connected to a damping mechanism which provides a resistance to the rocker arm mechanism. Each pedal mechanism is linked to a steel rope of a linking mechanism so that the pair of the pedal mechanisms can move back and forth against each other alternately along the non-parallel linear tracks. A handle is arranged on a top of each rocker arm mechanism, a user can exercise by holding the handles and treading on the pedal mechanism. | 06-17-2010 |
Patent application number | Description | Published |
20110256715 | BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide. | 10-20-2011 |
20120001262 | METAL CONDUCTOR CHEMICAL MECHANICAL POLISH - The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment. | 01-05-2012 |
20130192634 | BRUSH CLEANING SYSTEM - A plate with a static charge on a surface is used to clean a brush. The plate uses both static charge and mechanical force to remove particles from the surface of the brush to increase the useful life of the brush. | 08-01-2013 |
20130256659 | REDUCTION OF OCD MEASUREMENT NOISE BY WAY OF METAL VIA SLOTS - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches. | 10-03-2013 |
20140159243 | Metal Conductor Chemical Mechanical Polish - The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment. | 06-12-2014 |
20150024661 | MECHANISMS FOR REMOVING DEBRIS FROM POLISHING PAD - Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided. | 01-22-2015 |
20150087208 | APPARATUS AND METHOD FOR MANUFACTURING A SEMICONDUCTOR WAFER - In a semiconductor wafer manufacturing apparatus, a rotation module is provided to hold the semiconductor wafer at a plane. The semiconductor wafer is revolved by the rotation module around a first axis. The first axis is substantially perpendicular to the plane. A cleaning module is configured to revolve around a second axis when the cleaning module contacts the surface of the semiconductor wafer. A mechanism is further provided to enable the rotation module and/or the cleaning module to move along a direction substantially perpendicular to the first axis. Consequently, the relative velocities at the contact points between the semiconductor wafer and the cleaning module are changed. Moreover, no relative velocity at any contact point between the semiconductor wafer and the cleaning module is zero or close to zero. | 03-26-2015 |
Patent application number | Description | Published |
20130293827 | GLASSES FRAME - A glasses frame comprises a body and two temples. Each of the two temples includes a protruding portion, a rod extending downward from the protruding portion, and a guiding block formed at one end of the rod. The body is provided at each end thereof with a protruding portion, a pivot hole penetrating the protruding portion, a guiding groove in communication with the pivot hole, and a stop portion formed at a bottom of the guiding groove. The rods of the two temples are inserted downward into the pivot holes of the body respectively, and the guiding blocks move downward along the guiding grooves and slide over the stop portions and engage against the bottom of the protruding portions, respectively, so that the two temples are pivotally fixed at both ends of the body without using screws, which reduces manufacturing cost while making assembly easier. | 11-07-2013 |
20140071396 | EYEGLASSES - A pair of eyeglasses comprises two temples and a frame. Each temple is provided with a protrusion. Each end of the frame is defined with a notch, an elastic stopping piece protruded out of an inner wall of the notch, and a space formed between the stopping piece and the notch and provided for receiving the protrusion. The protrusion of the temple is located in the space by the elasticity of the stopping piece after pushing the stopping piece. And the elasticity of the stopping piece makes it restored and abutted against the protrusion, so as to prevent the protrusion from disengaging from the space. In addition, the temple can be pivoted to the frame without using bolts, which makes it easier to assemble and detach. | 03-13-2014 |
Patent application number | Description | Published |
20130024824 | Optical Proximity Correction Method - An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask. | 01-24-2013 |
20130280645 | Mask Set for Double Exposure Process and Method of Using the Mask Set - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 10-24-2013 |
20140258946 | MASK SET FOR DOUBLE EXPOSURE PROCESS AND METHOD OF USING THE MASK SET - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 09-11-2014 |
Patent application number | Description | Published |
20100146503 | SCHEDULER OF VIRTUAL MACHINE MODULE, SCHEDULING METHOD THEREFOR, AND DEVICE CONTAINING COMPUTER SOFTWARE - A scheduler of a virtual machine (VM) module, a scheduling method thereof, and a device containing computer software are provided. The scheduler has a classification module and a scheduling module. The classification module receives at least one VM module and analyzes a resource proportion parameter to generate classification result information. The scheduling module has a first schedule queue and a second schedule queue, sort an immediately resource-required VM module to the first schedule queue and a non immediately resource-required VM module to the second schedule queue, and determine whether the VM module of the first schedule queue exists or not, and if yes, it outputs the VM module of the first schedule queue to a processor; otherwise, outputs the VM module of the second schedule queue to the processor. | 06-10-2010 |
20120133640 | METHOD AND SYSTEM FOR COMBINING 2D IMAGE AND 3D MODEL AND COMPUTER PROGRAM PRODUCT THEREOF - A method and system for combining a 2D image and a 3D model and a computer program product thereof are provided. A corresponding relation between a general model and a 2D image is established. A system provides an operation interface. Next, functions provided by the operation interface include designating a feature point on the 2D image and specifying a confirmation point corresponding to the feature point on the general model. Finally, according to a viewpoint space vector of the general model, a display space vector of the 2D image is decided. Furthermore, when the operation interface displays the general model according to a specific viewpoint space vector, the 2D image having the corresponding display space vector is selected for display. | 05-31-2012 |
20120133753 | SYSTEM, DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT FOR FACIAL DEFECT ANALYSIS USING ANGULAR FACIAL IMAGE - A system, device, method, and computer program product for facial defect analysis using an angular facial image are provided. The system includes a storage module, an image angle detection module, a feature definition module, and a skin analysis module. The storage module stores at least one angular facial image, at least one skin defect condition, and at least one of multi-angle facial feature conditions. The image angle detection module detects an angle of the angular facial image. The feature definition module analyzes the angular facial image according to the facial feature conditions, so as to obtain at least one facial skin area image. The skin analysis module determines whether at least one skin defect image exists in the at least one facial skin area image by using the skin defect condition, and if yes, marks the at least one skin defect image in the at least one facial skin area image. | 05-31-2012 |
Patent application number | Description | Published |
20110291774 | EQUALIZER AND METHOD OF EQUALIZING SIGNALS - An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time. | 12-01-2011 |
20110292986 | CIRCUIT FOR RECOGNIZING A BEGINNING AND A DATA RATE OF DATA AND METHOD THEREOF - A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit . The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized. | 12-01-2011 |
20110293055 | CIRCUIT FOR GENERATING A CLOCK DATA RECOVERY PHASE LOCKED INDICATOR AND METHOD THEREOF - A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result. | 12-01-2011 |
20120121052 | PHASE SELECTOR CAPABLE OF TOLERATING JITTER AND METHOD THEREOF, AND CLOCK AND DATA RECOVERY CIRCUIT - A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal. | 05-17-2012 |
Patent application number | Description | Published |
20130059441 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value. | 03-07-2013 |
20130295738 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed. | 11-07-2013 |
20140306272 | METHOD OF FORMING A FINFET STRUCTURE - A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor. | 10-16-2014 |
20140308761 | Sidewall Image Transfer Process - A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed. | 10-16-2014 |
20140322883 | METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates. | 10-30-2014 |
20140367798 | NON-PLANAR TRANSISTOR - A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor. | 12-18-2014 |
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20090243904 | Randomized thermometer-coding digital-to-analog converter and method therefor - A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection. | 10-01-2009 |
20100134079 | ANALOG VARIABLE-FREQUENCY CONTROLLER AND SWITCHING CONVERTER THEREWITH - An analog variable-frequency controller includes a first current generator, a second current generator, a clock generator and a light/heavy load selector. The first and second current generator receive a load current signal and then output a first voltage signal and a second voltage signal, respectively. The clock generator generates a corresponding switching frequency according to the first voltage signal or the second voltage signal. The light/heavy load selector, connected with the first current generator, the second current generator and the clock generator, receives a control signal for controlling the clock generator to receive the first voltage signal or the second voltage signal. The abovementioned controller is implemented by an analog circuit, which has a lower circuit complexity, lower cost and is easy to be integrated into a switching converter. | 06-03-2010 |
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20130011808 | MOUNTING METHOD OF DENTAL CAST - A mounting method of dental cast is disclosed. The mounting method includes the steps of providing an articulator and a. label module having at least a label and at least a reference object, generating a label coordinate information in accordance with the reference object and the label, providing a midface and mandible image information and generating a landmark coordinate information in accordance with a plurality of landmarks of the midface and mandible image information, generating a structure coordinate information in accordance with a plurality of structures of the articulator and the label, disposing a first dental cast connected with the label module on the articulator, and providing a detecting device to detect the label and adjust the position of the first dental cast in accordance with the midface and mandible image information, the label coordinate information, and the structure coordinate information. | 01-10-2013 |
20130011809 | ORTHOGNATHIC PLANNING SYSTEM AND METHOD - An orthognathic planning system applied with at least a dental cast includes an articulator, a detecting device, at least a label module and a data processing device. The dental cast is mounted on the articulator. The detecting device is disposed with respect to the articulator. The label module has at least a label and is disposed on the dental cast. The data processing device is signally connected with the detecting device and stores midface and mandible image data. The detecting device traces the label and provides position data, and the data processing device provides orthognathic planning data in accordance with the position data and the midface and mandible image data. The present invention also discloses an orthognathic planning method. | 01-10-2013 |
20140017627 | AUXILIARY DEVICE FOR ARTICULATOR - An auxiliary device for an articulator includes a base and at least an adjusting structure. The base is provided for positioning an articulator, and the adjusting structure is disposed on the base. The adjusting structure includes a first ball joint, a second ball joint and a connecting assembly. The first ball joint is connected to the base, and the two ends of the connecting assembly are connected to the first ball joint and the second ball joint, respectively. The adjusting structure is moved relatively to the articulator by the movement of at least one of the first ball joint and the second ball joint, thereby adjusting the position of a dental cast disposed on the articulator. The auxiliary device is advantageous for conveniently adjusting the dental cast disposed on the articulator and accelerating the process of the preoperative planning. | 01-16-2014 |
20140322665 | GUIDING TEMPLATE FOR DENTAL IMPLANTOLOGY - A guiding template for dental implantology is disclosed. The guiding template includes a fixing base and at least one metallic ring. The fixing base has an inner side and an outer side, and the fixing base includes a guiding portion as an entry at the outer side. The guiding portion has a stopper. The metallic ring is disposed on the guiding portion. Besides, the metallic ring contacts against the stopper and penetrates through the fixing base to connect the outer side to the inner side. | 10-30-2014 |
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20130183801 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - A method for manufacturing semiconductor devices includes providing a substrate having a first region and a second region defined thereon, and a shallow trench isolation (STI) formed in between the first region and the second region, the first region comprising a first gate structure and the second region comprising a second gate structure respectively formed therein; forming a patterned protecting layer covering at least the entire STI and the second region on the substrate; forming recesses not exposing the STI in the substrate respectively at two sides of the first gate structure; and forming an epitaxial layer in the recesses respectively, the epitaxial layer filling up the recesses. | 07-18-2013 |
20130241002 | RESISTOR AND MANUFACTURING METHOD THEREOF - A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench. | 09-19-2013 |
20130270613 | METHOD OF TRIMMING SPACERS AND SEMICONDUCTOR STRUCTURE THEREOF - A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode. | 10-17-2013 |
20130307084 | RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE - A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench. | 11-21-2013 |
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20120139802 | Multi-band antenna - A multi-band antenna includes a loop conductor, a first conductor arm, and a second conductor arm. The loop conductor is configured to resonate in a first frequency band and includes a feed-in end for feeding of signals and a main body that extends from the feed-in end, and that has a grounding point disposed adjacent to the feed-in end. The first conductor arm is configured to resonate in a second frequency band and extends from the feed-in end. The second conductor arm is configured to resonate in a third frequency band and extends from the feed-in end. At least one of the loop conductor, the first conductor arm, and the second conductor arm is bent so as to be disposed in different planes. | 06-07-2012 |
20120146858 | MULTI-BAND ANTENNA MODULE - A multi-band antenna module is disposed in a housing of an electronic device. The housing has a grounding plane disposed therein and includes a metal frame part having two ends electrically connected to opposite side edges of the grounding plane. The multi-band antenna module includes a conductor, a substrate, a grounding section, and a first radiator section. The conductor is to be coupled across the metal frame part and the grounding plane so as to cooperate with the grounding plane and a portion of the metal frame part to form a closed loop thereamong, in which the substrate is disposed. The first radiator section and the grounding section are disposed on the substrate, with the grounding section to be coupled electrically to the grounding plane. A portion of the first radiator section is disposed to cooperate with the closed loop to resonate in a first frequency band. Another portion of the first radiator section is disposed to cooperate with the grounding section to resonate in a second frequency band. | 06-14-2012 |
20120154230 | MULTI-BAND ANTENNA - A multi-band antenna includes a feed-in section, a loop conductor, a first conductor arm, a second conductor arm, and a third conductor arm. The feed-in section includes a feed-in point for feeding of signals. The loop conductor extends from the feed-in section and has a grounding point disposed adjacent to the feed-in point. The first conductor arm is configured to resonate in a first frequency band and extends from the feed-in section. The second conductor arm is configured to resonate in a second frequency band and extends from the feed-in section. The third conductor arm is configured to resonate in a third frequency band and extends from the feed-in section. At least one of the loop conductor, the first conductor arm, the second conductor arm, and the third conductor arm is bent so as to be disposed in different planes. | 06-21-2012 |
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20100146503 | SCHEDULER OF VIRTUAL MACHINE MODULE, SCHEDULING METHOD THEREFOR, AND DEVICE CONTAINING COMPUTER SOFTWARE - A scheduler of a virtual machine (VM) module, a scheduling method thereof, and a device containing computer software are provided. The scheduler has a classification module and a scheduling module. The classification module receives at least one VM module and analyzes a resource proportion parameter to generate classification result information. The scheduling module has a first schedule queue and a second schedule queue, sort an immediately resource-required VM module to the first schedule queue and a non immediately resource-required VM module to the second schedule queue, and determine whether the VM module of the first schedule queue exists or not, and if yes, it outputs the VM module of the first schedule queue to a processor; otherwise, outputs the VM module of the second schedule queue to the processor. | 06-10-2010 |
20120143022 | PHYSIOLOGICAL SIGNAL DETECTION SYSTEM CAPABLE OF SHOWING EMOTIONS, DEVICE AND EMOTIONAL DISPLAY METHOD - A physiological signal detection system and device capable of showing emotions and an emotional display method are provided. The system includes: a display unit; a storage unit, for storing a plurality of conditions of emotional index; a physiological signal detection unit, for acquiring at least one physiological signal; a physiological signal recognition unit, for recognizing and filtering the at least one physiological signal; an emotional index operation unit, for generating a value of emotional index according to the at least one physiological signal; and a processing unit, for comparing the conditions of emotional index according to the value of emotional index to generate a comparison result and displaying a display signal corresponding to the value of emotional index on the display unit according to the comparison result. | 06-07-2012 |