Patent application number | Description | Published |
20110199843 | Strobe Offset in Bidirectional Memory Strobe Configurations - A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received. | 08-18-2011 |
20120300564 | Strobe Offset in Bidirectional Memory Strobe Configurations - A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received. | 11-29-2012 |
Patent application number | Description | Published |
20120191630 | Updateable Predictive Analytical Modeling - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets for predictive modeling can be received, e.g., over a network from a client computing system. The training data included in the training data sets is different from initial training data that was used with multiple training functions to train multiple trained predictive models stored in a predictive model repository. The series of training data sets are used with multiple trained updateable predictive models obtained from the predictive model repository and multiple training functions to generate multiple retrained predictive models. An effectiveness score is generated for each of the retrained predictive models. A first trained predictive model is selected from among the trained predictive models included in the predictive model repository and the retrained predictive models based on their respective effectiveness scores. | 07-26-2012 |
20120191631 | Dynamic Predictive Modeling Platform - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets are received and added to a training data queue. In response to a first condition being satisfied, multiple retrained predictive models are generated using the training data queue, multiple updateable trained predictive models obtained from a repository of trained predictive models, and multiple training functions. In response to a second condition being satisfied, multiple new trained predictive models are generated using the training data queue, at least some training data stored in a training data repository and training functions. The new trained predictive models include static trained predictive models and updateable trained predictive models. The repository of trained predictive models is updated with at least some of the retrained predictive models and new trained predictive models. | 07-26-2012 |
20120284212 | Predictive Analytical Modeling Accuracy Assessment - A system includes a computer(s) coupled to a data storage device(s) that stores a training function repository and a predictive model repository that includes includes updateable trained predictive models each associated with an accuracy score. A series of training data sets are received, being training samples each having output data that corresponds to input data. The training data is different from initial training data that was used with training functions from the repository to train the predictive models initially. Upon receiving a first training data set included in the series and for each predictive model in the repository, the input data in the first training set is used to generate predictive output data that is compared to the output data. Based on the comparison and previous comparisons determined from the initial training data and from previously received training data sets, an updated accuracy score for each predictive model is determined. | 11-08-2012 |
20120284213 | Predictive Analytical Modeling Data Selection - A system includes a computer(s) coupled to a data storage device(s) that stores a training data repository and a predictive model repository. The training data repository includes retained data samples from initial training data and from previously received data sets. The predictive model repository includes at least one updateable trained predictive model that was trained with the initial training data and retrained with the previously received data sets. A new data set is received. A richness score is assigned to each of the data samples in the set and to the retained data samples that indicates how information rich a data sample is for determining accuracy of the trained predictive model. A set of test data is selected based on ranking by richness score the retained data samples and the new data set. The trained predictive model is accuracy tested using the test data and an accuracy score determined. | 11-08-2012 |
20120284600 | PREDICTIVE MODEL APPLICATION PROGRAMMING INTERFACE - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for utilizing predictive models from an application scripting language. | 11-08-2012 |
20130144819 | SCORE NORMALIZATION - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for score normalization. One of the methods includes receiving initial training data, the initial training data comprising initial training records, each initial training record identifying input data as input and a category as output. The method includes generating a first trained predictive model using the initial training data and a training function. The method includes generating intermediate training records by inputting input data of the initial training records to a second trained predictive model, the second trained predictive model generated using the training function, each intermediate training record having a score. The method also includes generating a score normalization model using a score normalization training function and the intermediate training records. | 06-06-2013 |
20130346351 | ASSESSING ACCURACY OF TRAINED PREDICTIVE MODELS - A system includes a computer(s) coupled to a data storage device(s) that stores a training data repository and a predictive model repository. The training data repository includes retained data samples from initial training data and from previously received data sets. The predictive model repository includes at least one updateable trained predictive model that was trained with the initial training data and retrained with the previously received data sets. A new data set is received. A richness score is assigned to each of the data samples in the set and to the retained data samples that indicates how information rich a data sample is for determining accuracy of the trained predictive model. A set of test data is selected based on ranking by richness score the retained data samples and the new data set. The trained predictive model is accuracy tested using the test data and an accuracy score determined. | 12-26-2013 |
20140046880 | Dynamic Predictive Modeling Platform - Methods, systems, and apparatus, including computer programs encoded on one or more computer storage devices, for training and retraining predictive models. A series of training data sets are received and added to a training data queue. In response to a first condition being satisfied, multiple retrained predictive models are generated using the training data queue, multiple updateable trained predictive models obtained from a repository of trained predictive models, and multiple training functions. In response to a second condition being satisfied, multiple new trained predictive models are generated using the training data queue, at least some training data stored in a training data repository and training functions. The new trained predictive models include static trained predictive models and updateable trained predictive models. The repository of trained predictive models is updated with at least some of the retrained predictive models and new trained predictive models. | 02-13-2014 |
20150186800 | Predictive Model Evaluation and Training Based on Utility - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training a plurality of different types of predictive models using training data, wherein each of the predictive models implements a different machine learning technique. One or more weights are obtained wherein each weight is associated with an answer category in the plurality of examples. A weighted accuracy is calculated for each of the predictive models using the one or more weights. | 07-02-2015 |
Patent application number | Description | Published |
20130001741 | INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD - Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path. | 01-03-2013 |
20150091097 | HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT - Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor. | 04-02-2015 |
20150102826 | DESIGN STRUCTURES AND METHODS FOR EXTRACTION OF DEVICE CHANNEL WIDTH - Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths. | 04-16-2015 |
20150130026 | PRINTING MINIMUM WIDTH FEATURES AT NON-MINIMUM PITCH AND RESULTING DEVICE - Methods for forming a semiconductor layer, such as a metal | 05-14-2015 |
20160093565 | PRINTING MINIMUM WIDTH FEATURES AT NON-MINIMUM PITCH AND RESULTING DEVICE - Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape. | 03-31-2016 |
Patent application number | Description | Published |
20120299106 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device is provided that includes a first inverter having a first p-channel FinFET and a first n-channel FinFET each coupled to a first shared contact forming a first cell node and having a first common gate. A second inverter is included having a second p-channel FinFET and a second n-channel FINFET each coupled to a second shared contact forming a second cell node and having a second common gate aligned with the first shared contact of the first inverter forming a latch circuit. Additionally, a pair of FinFET passgates are included each having a drain contact respectively coupled the first and second cell nodes and a source contact connected to one of a complementary bit line. Finally, a word line is connected to a gate contact of each of the pair of FinFET passgates to provide a static random access memory cell. | 11-29-2012 |
20130107608 | SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL | 05-02-2013 |
20130107610 | SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL | 05-02-2013 |
20130242645 | Memory Cell - Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors. | 09-19-2013 |
20130293250 | INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES - An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress. | 11-07-2013 |
20130332136 | MODELING MEMORY CELL SKEW SENSITIVITY - A method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result. | 12-12-2013 |
20130341723 | MEMORY CELL WITH ASYMMETRIC READ PORT TRANSISTORS - A memory cell includes a storage element and a read port. The read port includes a first transistor having a first gate coupled to the storage element, a first source region, and a first drain region. The second transistor includes a second gate, a second source region coupled to the first drain region, and a second drain region. A first dopant profile of the first and second source regions is asymmetric with respect to a second dopant profile of the first and second drain regions. | 12-26-2013 |
20140021579 | INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD - Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path. | 01-23-2014 |
20150147857 | MEMORY CELL - Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional, gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors. | 05-28-2015 |
20160025805 | WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES - Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure. | 01-28-2016 |