Patent application number | Description | Published |
20110274784 | METHOD OF CONTINUOUSLY PRODUCING EDIBLE LIPID-BASED COMPOSITION - The present invention provides a method of continuously producing edible lipid-based composition, including the steps: preparing alcohol and organic acid in a predetermined ratio and a reaction tank received with immobilized | 11-10-2011 |
20120083592 | CONTINUOUS PREPARATION METHOD OF GINSENG GINSENOSIDES AND POLYSACCHARIDES - The present invention provides a continuous preparation method of ginseng ginsenosides and polysaccharides, whereby the ginseng extract liquor and supercritical solvent are poured continuously into a separation tank at 10-30 MPa and 40-60° C. as well as a preset flow rate; so the ginseng extract liquor can be separated in the separation tank to obtain ginsenosides and polysaccharides at different positions of the separation tank. | 04-05-2012 |
20120309947 | METHOD AND SYSTEM FOR CONTINUOUS SEPARATION AND PURIFICATION OF GINSENOSIDES - The present invention provides a method and system for continuous separation and purification of ginsenosides, whereby supercritical fluid technology is used to feed Ginseng extract liquor and supercritical solvent continuously into a separation tank at 20-30 Mpa and 40-60° C., such that ginsenosides can be separated from Ginseng extract liquor; then, ginsenosides are continuously fed to a purifying tank for obtaining highly pure ginsenosides; this system comprising: a holding tank, used to accommodate Ginseng extract liquor; a separation tank, connected with the holding tank, fitted with an electric heater, and used to separate ginsenosides from Ginseng extract liquor; a supercritical fluid vessel, connected with the separation tank to provide supercritical fluid; a high-pressure metering pump, connected between the supercritical fluid vessel and separation tank; a reactant metering pump, connected between the holding tank and separation tank; a precooler, connected between the supercritical fluid vessel and high-pressure metering pump; two preheaters, connected separately between the high-pressure metering pump, reactant metering pump and separation tank; a purifying tank, connected with the separation tank, fitted with an electric heater, and used to purify ginsenosides; two temperature controllers, connected separately with the electric heater in the separation tank and purifying tank. | 12-06-2012 |
20130075336 | METHOD AND SYSTEM FOR CONTINUOUS SEPARATION AND PURIFICATION OF GANODERIC ACIDS AND POLYSACCHARIDES - The present invention provides a method and system for continuous separation and purification of ganoderic acids and polysaccharides, which, via the help of supercritical fluid technology, could feed continuously | 03-28-2013 |
20130287927 | PREPARATION METHOD AND SYSTEM FOR CLARIFIED PLUM WINE AND PLUM EXTRACT - The present invention provides a preparation method and system for clarified plum wine and plum extract, blanching plum at 95° C. for 5 minutes, and then extracting the blanched plum with extracting solution containing 70-75% alcohol in volume ratio of 1:2 (w/v) at 8˜10° C. in vacuum for 30 minutes before centrifugation, cooling clarification of the plum juice at −8° C. and −20° C. is carried out immediately for 30 minutes respectively, so as to obtain clarified plum wine. Afterwards, the plum wine is concentrated in vacuum to ⅕ of original volume to obtain clarified plum extract; therefore, high quality plum wine and plum extract can be obtained without destroying the plum tissue, and the production efficiency is quite ideal. | 10-31-2013 |
20130289300 | METHOD AND SYSTEM FOR SEPARATING LINALYL ACETATE FROM LAVENDER ESSENTIAL OIL AND PREPARING ITS DERIVATIVES - The present invention provides a method and system for separating linalyl acetate from Lavender essential oil and preparing its derivatives, whereby the supercritical fluid technology is used to feed Lavender essential oil and supercritical solvent into the first separating tank, where linalyl acetate and linalool are separated from Lavender essential oil; then linalyl acetate is conveyed to the second separating tank, where linalyl acetate is separated with wax-containing oily substance to obtain high-concentration linalyl acetate; next linalool and vitamin C solution are conveyed to a reaction tank for esterification synthesis, and the reaction tank is filled with acid resin catalyst to obtain linalool-vitamin C derivative; with this design, it is possible to reduce the nervous tension, and adjust high-concentration linalyl acetate affecting physiological and psychological stress, as well as vitamin C derivative with anti-oxidizing oily fragrance. | 10-31-2013 |
20140128582 | CONTINUOUS PREPARATION METHOD OF GINSENG GINSENOSIDES AND POLYSACCHARIDES - The present invention provides a continuous preparation method of | 05-08-2014 |
Patent application number | Description | Published |
20100242112 | SYSTEM AND METHOD FOR PROTECTING NETWORK RESOURCES FROM DENIAL OF SERVICE ATTACKS - The present disclosure generally pertains to systems and methods for protecting network resources from denial of service attacks. In one exemplary embodiment, a responder stores an access filter value used to determine whether an incoming message frame has been transmitted from an authorized user. In this regard, a user communication device includes logic for determining the access filter value stored at the responder and includes the access filter value in a message frame transmitted from the computer to the responder. The responder compares the received access filter value to the stored access filter value. If such values match or otherwise correspond, the responder authenticates the message frame. However, if such values do not match or otherwise correspond, the responder discards the message frame. Thus, the responder processes authenticated message frames and discards unauthenticated message frames thereby preventing denial of service attacks from malicious users. | 09-23-2010 |
20110099630 | SYSTEM AND METHOD FOR PROTECTING COMMUNICATION DEVICES FROM DENIAL OF SERVICE ATTACKS - A system for preventing successful denial of service attacks comprises a first communication device, a second communication device, and a network. The first and second communication devices establish a communication session via the network. Based on various information, such as a pre-shared secret, one of the communication devices determines a network access filter value and compares this value to at least one data frame in order to authenticate such data frame without committing significant computing resource and any memory space. By updating the network access filter over time, an unauthorized user who discovers the outdated network access filter values is prevented from successfully launching a denial of service attack. | 04-28-2011 |
20120124383 | SYSTEM AND METHOD FOR PROTECTING NETWORK RESOURCES FROM DENIAL OF SERVICE ATTACKS - The present disclosure generally pertains to systems and methods for protecting network resources from denial of service attacks. In one exemplary embodiment, a responder stores an access filter value used to determine whether an incoming message frame has been transmitted from an authorized user. In this regard, a user communication device includes logic for determining the access filter value stored at the responder and, includes the access filter value in a message frame transmitted from the computer to the responder. The responder compares the received access filter value to the stored access filter value. If such values match or otherwise correspond, the responder authenticates the message frame. However, if such values do not match or otherwise correspond, the responder discards the message frame. Thus, the responder processes authenticated message frames and discards unauthenticated message frames thereby preventing denial of service attacks from malicious users. | 05-17-2012 |
Patent application number | Description | Published |
20130316510 | METHOD OF FORMING A RESIST PATTERN WITH MULTIPLE POST EXPOSURE BAKING STEPS - A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer. | 11-28-2013 |
20130323898 | METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER - A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process. | 12-05-2013 |
20140065554 | Method and Apparatus for Developing Process - The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical. | 03-06-2014 |
20140120459 | METHOD FOR IMPROVING RESIST PATTERN PEELING - A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout. | 05-01-2014 |
Patent application number | Description | Published |
20080225939 | MULTIFUNCTIONAL VIDEO ENCODING CIRCUIT SYSTEM - The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system. | 09-18-2008 |
20120112810 | CLOCK DE-SKEWING DELAY LOCKED LOOP CIRCUIT - A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%. | 05-10-2012 |
20130258795 | SINGLE-ENDED READ RANDOM ACCESS MEMORY - A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. | 10-03-2013 |
20130314977 | MEMORY CIRCUIT PROPERLY WORKABLE UNDER LOW WORKING VOLTAGE - A memory circuit properly workable under low working voltage includes a plurality of write word lines, a plurality of write bit lines, a plurality of read/write word lines, a plurality of read/write bit lines, a plurality of read/write inverted word lines, a plurality of virtual voltage source circuits, a plurality of virtual ground circuits, and a plurality of asymmetrical RAM cells constituting a cell array. The asymmetrical RAM cells are formed of seven transistors, five of which are NMOS transistors and two of which are PMOS transistors. The virtual voltage power source circuit and the virtual ground circuit can reinforce the write-in and read abilities under low working voltage to make the write-in and read actions more stable, decrease leakage current, and lower power consumption. | 11-28-2013 |
Patent application number | Description | Published |
20110220980 | MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME - A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F | 09-15-2011 |
20130015551 | METHOD FOR FABRICATING MEMORY DEVICE WITH BURIED DIGIT LINES AND BURIED WORD LINESAANM Wang; Kuo-ChenAACI Chiayi CityAACO TWAAGP Wang; Kuo-Chen Chiayi City TW - A method for fabricating a memory array includes providing a semiconductor substrate having thereon a plurality of line-shaped active areas and intermittent line-shaped trench isolation regions between the plurality of line-shaped active areas, which extend along a first direction; forming buried word lines extending along a second direction in the semiconductor substrate, the buried word lines intersecting with the line-shaped active areas and the intermittent line-shaped trench isolation regions, wherein the second direction is not perpendicular to the first direction; forming buried digit lines extending along a third direction in the semiconductor substrate, wherein the third direction is substantially perpendicular to the second direction; and forming storage nodes at storage node sites between the buried digit lines. | 01-17-2013 |
20130314967 | MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME - A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F | 11-28-2013 |
Patent application number | Description | Published |
20080316854 | Microfluid mixer - A microfluid mixer is provided. The non-linear electrokineticsis is applied to the design of the microfluid mixer. The microfluid mixer comprises a first and a second microfluidic elements, a mixing reservoir, and a micro channel unit, wherein the micro channel unit has at least two control channels for respectively connecting the first and the second microfluidic elements and the mixing reservoir. When two microfluids are mixed in the mixing reservoir, the electro-osmosis fluid field of the microfluids in the control channel of the mixing reservoir is changed by applying AC signal, such that powerful chaotic mixing effect is therefore produced by the two microfluids in the mixing reservoir. | 12-25-2008 |
20090190877 | MICROFLUIDIC DEVICE WITH MICROSTRUCTURE, AND SENSING SYSTEM AND METHOD USING SAME - A microfluidic device with microstructure includes a channel for accommodating an electrolytic solution therein and at least one microstructure formed in the channel. When an alternating-current signal is input to the microfluidic device so that a surface of the microstructure is polarized by a generated electric field, ions having polarity reverse to that of an electrolytic solution will migrate to the surface of the microstructure to form a field-induced electrical double layer to result in electro-osmotic flows at the corners at two sides of the microstructure, which causes formation of relatively fierce circular vortices in the solution. A sensing system and a sensing method using the microfluidic device with microstructure are also disclosed. | 07-30-2009 |
20090277792 | Method for concentrating charged particles and apparatus thereof - The present invention discloses a method for concentrating charged particles and an apparatus thereof. The method comprises: providing a substrate comprising a reservoir; disposing a conducting granule in the reservoir, the conducting granule being negatively charged or positively charged and comprising nano-pores or nano-channels capable of permitting ion permeation; disposing a buffer solution in the reservoir, the buffer solution comprising counter-ions having an opposite electric property to the conducting granule; adding the charged particles into the buffer solution, the charged particles being co-ions having an identical electric property as the conducting granule; and applying an external electric field on the conducting granule. While the external electric field is applied on the conducting granule, the counter-ions exit from the nano-pores or nano-channels and have a nonuniform concentration on a surface of the conducting granule such that a transient ion super-concentration phenomenon occurs at an ejecting pole on the conducting granule. Hence the present invention has potential application in bead-based molecular assays. | 11-12-2009 |
20100264040 | METHOD FOR CONCENTRATING PARTICLES OR MOLECULES AND APPARATUS THEREOF - The present invention provides a method for concentrating particles or molecules and an apparatus thereof. The apparatus comprises a substrate, a conducting granule having nano-pores or nano-channels capable of permitting ion permeation, an electrolyte solution comprising counter-ions having an opposite electric property to the conducting granule, and an external field. Wherein, particles or molecules to be concentrated have an identical electric property as the conducting granule at a predefined pH value, and are added into the electrolyte solution with the predefined pH value. While the external electric field is applied across the reservoir where the conducting granule is sitting, the counter-ions exit from the nano-pores or nano-channels and such that a transient ion super-concentration phenomenon occurs at an ejecting pole on the conducting granule so as to concentrate the particles or molecules. Hence the present invention has potential application in bead-based molecular assays. | 10-21-2010 |
20110294225 | Method for Detecting Optical Signals, Microfluidic Mixing Chip Having Light Emitting Compound and System Thereof - A method for detecting optical signals, a microfluidic mixing chip having light emitting compound and a system thereof are provided. The microfluidic mixing system comprises the microfluidic mixing chip, an electrode pairs and a power supplier. The microfluidic mixing chip comprises a first side cavity, a second side cavity and a mixing cavity. The mixing cavity is disposed between the first side cavity and the second side cavity. The mixing cavity further contains the light emitting compound, a catalyst and a redox reagent. The electrode pair is respectively disposed to the first side cavity and the second cavity. The power supplier supplies a power source with high frequency alternating current electric field. By utilizing the power source with alternating current electric field, the light emitting compound, the redox reagent and the catalyst are mixed in the mixing cavity to generate a chemiluminescence or bioluminescence optical signal to detect. | 12-01-2011 |
20130122608 | Method for Estimating Binding Kinetic Rate Constants by Using Fiber Optics Particle Plasmon Resonance (FOPPR) Sensor - A method for estimating binding kinetic rate constants by using a fiber optic particle plasmon resonance (FOPPR) sensor mainly employs the steps of: providing a FOPPR sensor instrument system, obtaining optical signal intensities at an initial time and steady state signal intensities of first and second regions in an intensity versus time graph separately, substituting the measured signal intensity values into a formula derived by using a pseudo-first order rate equation model. According to this method, no fluorophore labeling is required. In addition, this method measures a temporal signal intensity evolution under static conditions as the samples are quickly loaded. As a result, unlike the conventional device where the sample is continuously infused, the method is able to measure binding and decomposition rate constants whose upper limit is not limited by a sample flow rate. | 05-16-2013 |
20140051188 | METHOD FOR OBTAINING BINDING KINETIC RATE CONSTANTS USING FIBER OPTIC PARTICLE PLASMON RESONANCE (FOPPR) SENSOR - A method for obtaining the binding kinetic rate constants using fiber optic particle plasmon resonance (FOPPR) sensor, suitable for a test solution with two or more concentrations, which employs the following major steps: providing one FOPPR sensor instrument system, obtaining optical time-resolved signal intensities starting at the initial time to the steady state of the two or more regions, substituting the measured signal intensity values into the formula which is derived by using the pseudo-first order rate equation model. In addition, this method measures the temporal signal intensity evolution under static conditions as the samples are quickly loaded. As a result, unlike the conventional device where the sample is continuously infused, the method is able to measure the association and dissociation rate constants of which the upper bounds are not limited by the sample flow rate. | 02-20-2014 |