Mattausch
Alfred Mattausch, Altmunster AT
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20090124745 | Particles of Precipitated Calcium Carbonate, Process For Making The Particles And Use Of The Particles As Filler - Particles of precipitated calcium carbonate with a rhombohedral crystal morphology exhibiting a low sodium content and a particle size distribution with a low cutoff value. Process for making such particles. Use of the particles as filler in polymer films. | 05-14-2009 |
Goesta Mattausch, Ullersdorf DE
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20090184262 | DEVICE AND METHOD FOR ALTERING THE CHARACTERISTICS OF THREE-DIMENSIONAL SHAPED PARTS USING ELECTRONS AND USE OF SAID METHOD - The invention relates to a device and a method for altering the characteristics of a three-dimensional molded part by means of electrons, including at least one electron accelerator for generating accelerated electrons and two electron exit windows, wherein the two electron exit windows are arranged opposite one another, wherein the two electron exit windows and at least one reflector delimit a process chamber in which the surface or an edge layer of the molded part are bombarded with electrons, wherein an energy density distribution inside the process chamber can be detected at least over one spatial dimension by means of a sensor system. | 07-23-2009 |
20110318498 | Coaxial Hollow Cathode Plasma Assisted Directed Vapor Deposition and Related Method Thereof - A plasma generation process that is more optimized for vapor deposition processes in general, and particularly for directed vapor deposition processing. The features of such an approach enables a robust and reliable coaxial plasma capability in which the plasma jet is coaxial with the vapor plume, rather than the orthogonal configuration creating the previous disadvantages. In this way, the previous deformation of the vapor gas jet by the work gas stream of the hollow cathode pipe can be avoided and the carrier gas consumption needed for shaping the vapor plume can be significantly decreased. | 12-29-2011 |
20130162134 | DEVICE FOR PRODUCING AN ELECTRON BEAM - The invention relates to a device for producing an electron beam, comprising a housing ( | 06-27-2013 |
Gösta Mattausch, Ullersdorf DE
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20140354149 | APPARATUS FOR GENERATING A HOLLOW CATHODE ARC DISCHARGE PLASMA - An apparatus for generating a hollow cathode arc discharge plasma, including two plasma sources, each including a hollow cathode and an electrode which is associated with the hollow cathode and which has an opening that extends through the electrode, wherein the hollow cathodes of the two plasma sources are connected to a pulse generator which generates a bipolar, medium-frequency pulsed voltage between the two hollow cathodes. Here, in each of the two plasma sources, the hollow cathode is connected in an electrically conducting manner, directly or with interconnection of at least one current direction limiting component, to the associated electrode. | 12-04-2014 |
Hans Juergen Mattausch, Higashihiroshima-Shi JP
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20100189351 | COMPRESSION PROCESSING APPARATUS AND COMPRESSION PROCESSING METHOD - A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets. | 07-29-2010 |
20120188811 | ASSOCIATIVE MEMORY - An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data. | 07-26-2012 |
Hans Juergen Mattausch, Hiroshima JP
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20090141531 | ASSOCIATIVE MEMORY AND SEARCHING SYSTEM USING THE SAME - Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times. | 06-04-2009 |
20100085790 | AMPLIFIER CIRCUIT AND ASSOCIATIVE MEMORY - An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI | 04-08-2010 |
20100202684 | IMAGE SEGMENTATION APPARATUS AND IMAGE SEGMENTATION METHOD - A pixel-value detecting circuit ( | 08-12-2010 |
20130114322 | ASSOCIATIVE MEMORY - An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT | 05-09-2013 |
Hans Juergen Mattausch, Hiroshima DE
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20100202178 | OFFSET REMOVAL CIRCUIT, ASSOCIATIVE MEMORY INCLUDING THE SAME, AND OFFSET VOLTAGE REMOVAL METHOD - An offset removal circuit ( | 08-12-2010 |
Hans Jurgen Mattausch, Higashihiroshima-Shi JP
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20080222360 | MULTI-PORT INTEGRATED CACHE - A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port. | 09-11-2008 |
Hans Jürgen Mattausch, Hiroshima JP
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20100179976 | SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING - A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data. | 07-15-2010 |
Hans Jürgen Mattausch, Hiroshima JP
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20100179976 | SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING - A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data. | 07-15-2010 |