Patent application number | Description | Published |
20090313193 | HIERARCHICAL TEMPORAL MEMORY SYSTEM WITH HIGHER-ORDER TEMPORAL POOLING CAPABILITY - A temporal pooler for a Hierarchical Temporal Memory network is provided. The temporal pooler is capable of storing information about sequences of co-occurrences in a higher-order Markov chain by splitting a co-occurrence into a plurality of sub-occurrences. Each split sub-occurrence may be part of a distinct sequence of co-occurrences. The temporal pooler receives the probability of spatial co-occurrences in training patterns and tallies counts or frequency of transitions from one sub-occurrence to another sub-occurrence in a connectivity matrix. The connectivity matrix is then processed to generate temporal statistics data. The temporal statistics data is provided to an inference engine to perform inference or prediction on input patterns. By storing information related to a higher-order Markov model, the temporal statistics data more accurately reflects long temporal sequences of co-occurrences in the training patterns. | 12-17-2009 |
20110225108 | TEMPORAL MEMORY USING SPARSE DISTRIBUTED REPRESENTATION - A processing node in a temporal memory system includes a spatial pooler and a sequence processor. The spatial pooler generates a spatial pooler signal representing similarity between received spatial patterns in an input signal and stored co-occurrence patterns. The spatial pooler signal is represented by a combination of elements that are active or inactive. Each co-occurrence pattern is mapped to different subsets of elements of an input signal. The spatial pooler signal is fed to a sequence processor receiving and processed to learn, recognize and predict temporal sequences in the input signal. The sequence processor includes one or more columns, each column including one or more cells. A subset of columns may be selected by the spatial pooler signal, causing one or more cells in these columns to activate. | 09-15-2011 |
20130054495 | ENCODING OF DATA FOR PROCESSING IN A SPATIAL AND TEMPORAL MEMORY SYSTEM - A spatial and temporal memory system (STMS) processes input data to detect whether spatial patterns and/or temporal sequences of spatial patterns exist within the data, and to make predictions about future data. The data processed by the STMS may be retrieved from, for example, one or more database fields and is encoded into a distributed representation format using a coding scheme. The performance of the STMS in predicting future data is evaluated for the coding scheme used to process the data as performance data. The selection and prioritization of STMS experiments to perform may be based on the performance data for an experiment. The best fields, encodings, and time aggregations for generating predictions can be determined by an automated search and evaluation of multiple STMS systems. | 02-28-2013 |
20130054496 | ASSESSING PERFORMANCE IN A SPATIAL AND TEMPORAL MEMORY SYSTEM - A spatial and temporal memory system (STMS) processes input data to detect whether spatial patterns and/or temporal sequences of spatial patterns exist within the data, and to make predictions about future data. The data processed by the STMS may be retrieved from, for example, one or more database fields and is encoded into a distributed representation format using a coding scheme. The performance of the STMS in predicting future data is evaluated for the coding scheme used to process the data as performance data. The selection and prioritization of STMS experiments to perform may be based on the performance data for an experiment. The best fields, encodings, and time aggregations for generating predictions can be determined by an automated search and evaluation of multiple STMS systems. | 02-28-2013 |
20130054552 | AUTOMATED SEARCH FOR DETECTING PATTERNS AND SEQUENCES IN DATA USING A SPATIAL AND TEMPORAL MEMORY SYSTEM - A spatial and temporal memory system (STMS) processes input data to detect whether spatial patterns and/or temporal sequences of spatial patterns exist within the data, and to make predictions about future data. The data processed by the STMS may be retrieved from, for example, one or more database fields and is encoded into a distributed representation format using a coding scheme. The performance of the STMS in predicting future data is evaluated for the coding scheme used to process the data as performance data. The selection and prioritization of STMS experiments to perform may be based on the performance data for an experiment. The best fields, encodings, and time aggregations for generating predictions can be determined by an automated search and evaluation of multiple STMS systems. | 02-28-2013 |
20140310226 | Time Aggregation and Sparse Distributed Representation Encoding for Pattern Detection - A spatial and temporal memory system (STMS) processes input data to detect whether spatial patterns and/or temporal sequences of spatial patterns exist within the data, and to make predictions about future data. The data processed by the STMS may be retrieved from, for example, one or more database fields and is encoded into a distributed representation format using a coding scheme. The performance of the STMS in predicting future data is evaluated for the coding scheme used to process the data as performance data. The selection and prioritization of STMS experiments to perform may be based on the performance data for an experiment. The best fields, encodings, and time aggregations for generating predictions can be determined by an automated search and evaluation of multiple STMS systems. | 10-16-2014 |
20140310227 | Pattern Detection Feedback Loop for Spatial and Temporal Memory Systems - A spatial and temporal memory system (STMS) processes input data to detect whether spatial patterns and/or temporal sequences of spatial patterns exist within the data, and to make predictions about future data. The data processed by the STMS may be retrieved from, for example, one or more database fields and is encoded into a distributed representation format using a coding scheme. The performance of the STMS in predicting future data is evaluated for the coding scheme used to process the data as performance data. The selection and prioritization of STMS experiments to perform may be based on the performance data for an experiment. The best fields, encodings, and time aggregations for generating predictions can be determined by an automated search and evaluation of multiple STMS systems. | 10-16-2014 |
Patent application number | Description | Published |
20100318783 | SERVICE ACTIVATION USING ALGORITHMICALLY DEFINED KEY - Systems and methods for service activation using algorithmically defined keys are disclosed. A consumer who has a relationship with a first party may wish to enroll in a service provided by a third party. The first party can maintain control of such enrollments through the use of algorithmically defined keys. The algorithmically defined keys also allow the third party service provider to verify data provided by the consumer as matching data stored by the first party. The verification provides for data synchronization without requiring the third party to have access to the first parties data systems. | 12-16-2010 |
20110238553 | ELECTRONIC ACCOUNT-TO-ACCOUNT FUNDS TRANSFER - Funds are electronically transferred between a provider and a beneficiary. A provider accountholder accesses a funds transfer system to communicate with a host. The provider accountholder sends the host information sufficient to process the electronic funds transfer including designating transfer conditions to be satisfied prior to remittance of the funds from a provider account to a beneficiary account. The host receives the funds transfer request from the provider accountholder, receives authorization of the funds transfer from the issuer of the provider account, and, prior to remitting the funds, determines if the transfer conditions are satisfied. In some implementations, the funds are suspended in the provider account or transferred to a temporary account before the remittance. A system is disclosed for generating a payment card for any beneficiary account type, where the funds transfers terminates in a new account opening, followed by funding of that new account. | 09-29-2011 |
20110282780 | METHOD AND SYSTEM FOR DETERMINING FEES AND FOREIGN EXCHANGE RATES FOR A VALUE TRANSFER TRANSACTION - A method for a value transfer operation includes determining a sender currency using the account information of the sender and a receiver currency using the BIN associated with the sender account. The method further includes determining a currency exchange rate, transaction fee, and currency markup fee based on the sender and receiver currencies and various attributes of the sender account and the receiver account. | 11-17-2011 |
20140325606 | SERVICE ACTIVATION USING ALGORITHMICALLY DEFINED KEY - Systems and methods for service activation using algorithmically defined keys are disclosed. A consumer who has a relationship with a first party may wish to enroll in a service provided by a third party. The first party can maintain control of such enrollments through the use of algorithmically defined keys. The algorithmically defined keys also allow the third party service provider to verify data provided by the consumer as matching data stored by the first party. The verification provides for data synchronization without requiring the third party to have access to the first parties data systems. | 10-30-2014 |
Patent application number | Description | Published |
20110169522 | FAULT-TOLERANT MULTI-CHIP MODULE - A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components. | 07-14-2011 |
20130003310 | CHIP PACKAGE TO SUPPORT HIGH-FREQUENCY PROCESSORS - A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip. | 01-03-2013 |
20130039661 | ECHELLE GRATING WITH CYCLIC FREE-SPECTRAL RANGE - An optical de-multiplexer (de-MUX) that includes an optical device that images and diffracts an optical signal using a reflective geometry is described, where a free spectral range (FSR) of the optical device associated with a given diffraction order abuts FSRs associated with adjacent diffraction orders. Moreover, the channel spacings within diffraction orders and between adjacent diffraction orders are equal to the predefined channel spacing associated with the optical signal. As a consequence, the optical device has a comb-filter output spectrum, which reduces a tuning energy of the optical device by eliminating spectral gaps between diffraction orders of the optical device. | 02-14-2013 |
20130121635 | DIRECT INTERLAYER OPTICAL COUPLER - In an MCM, an optical signal is conveyed by an optical waveguide disposed on a surface of a first substrate to an optical coupler having a vertical facet. This optical coupler has an optical mode that is different than the optical mode of the optical waveguide. For example, the spatial extent of the optical mode associated with the optical coupler may be larger, thereby reducing optical losses and sensitivity to alignment errors. Then, the optical signal is directly coupled from the vertical facet to a facing vertical facet of an identical optical coupler on another substrate, and the optical signal is conveyed in another optical waveguide disposed on the other substrate. | 05-16-2013 |
20130156366 | EFFICIENT INTER-CHIP OPTICAL COUPLING - In an MCM, an optical signal is conveyed by an optical waveguide disposed on a surface of a first substrate to a first optical coupler. This first optical coupler redirects the optical signal out of the plane of the optical waveguide. Then, an optical interposer guides the optical signal between the first optical coupler and a second optical coupler on a surface of a second substrate, thereby reducing spatial expansion of the optical signal between the optical couplers. Moreover, the second optical coupler redirects the optical signal into a plane of an optical waveguide disposed on a surface of the second substrate, which then conveys the optical signal. | 06-20-2013 |
20130230272 | CHIP ASSEMBLY CONFIGURATION WITH DENSELY PACKED OPTICAL INTERCONNECTS - A chip assembly configuration includes an substrate with an integrated circuit on one side and a conversion mechanism on the other side. The integrated circuit and the conversion mechanism are electrically coupled by a short electrical transmission line through the substrate. Moreover, the conversion mechanism converts signals between an electrical and an optical domain, thereby allowing high-speed communication between the integrated circuit and other components and devices using optical communication (for example, in an optical fiber or an optical waveguide). | 09-05-2013 |
20130265624 | SURFACE-NORMAL OPTICAL COUPLING USING A HOLOGRAPHIC RECORDING MATERIAL - An integrated circuit includes a holographic recording material substantially filling a cavity in a semiconductor layer. During operation of the integrated circuit, a holographic pattern in the holographic recording is reconstructed and used to diffract an optical signal propagating in a plane of an optical waveguide, which is defined in the semiconductor layer out of the plane through the cavity. In this way, the holographic recording material may be used to couple the optical signal to an optical fiber or another integrated circuit. | 10-10-2013 |
Patent application number | Description | Published |
20130126886 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer. | 05-23-2013 |
20130127006 | GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE - A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer. | 05-23-2013 |
20130146885 | Vertical GaN-Based Metal Insulator Semiconductor FET - A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers. | 06-13-2013 |
20130161705 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 06-27-2013 |
20140051236 | GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE - A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer. | 02-20-2014 |
20140370669 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 12-18-2014 |
20140374769 | GAN-BASED SCHOTTKY BARRIER DIODE WITH ALGAN SURFACE LAYER - A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas. | 12-25-2014 |
20150340514 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 11-26-2015 |
Patent application number | Description | Published |
20130032814 | METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS - A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface. | 02-07-2013 |
20130075748 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 03-28-2013 |
20130126884 | ALUMINUM GALLIUM NITRIDE ETCH STOP LAYER FOR GALLIUM NITRIDE BASES DEVICES - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 05-23-2013 |
20140162416 | ALUMINUM GALLIUM NITRIDE ETCH STOP LAYER FOR GALLIUM NITRIDE BASED DEVICES - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 06-12-2014 |
20150017792 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 01-15-2015 |
Patent application number | Description | Published |
20150137895 | QUADRATURE-BASED INJECTION LOCKING OF RING OSCILLATORS - Technologies are generally described for quadrature-based injection-locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator and used to determine a mean quadrature error (MQE) that characterizes the difference in frequency between the external signal and the ring oscillator's natural frequency. A control signal may then be generated from the MQE and used to adjust the ring oscillator natural frequency to reduce the difference between the ring oscillator natural frequency and the external signal. | 05-21-2015 |
20150139257 | NON-LINEAR VERTICAL-CAVITY SURFACE-EMITTING LASER EQUALIZATION - Technologies are generally described for implementing non-linear VCSEL equalization. In some examples, a rising edge tap parameter, a falling edge tap parameter, an equalization delay and a bias current may be used to equalize a data signal to be output from a VCSEL. A VCSEL model may be used to derive a VCSEL response to one or more isolated data pulses. The derived response may then be used to determine the rising and falling edge tap parameters and an equalization delay, based on a bias current value for the VCSEL and a data rate associated with the data signal. The data signal may then be adjusted based on the equalization delay and the rising and falling edge tap parameter and sent to the VCSEL for output. At the same time, the VCSEL may be biased with a bias current having the bias current value. | 05-21-2015 |
20150288144 | NON-LINEAR VERTICAL-CAVITY SURFACE-EMITTING LASER EQUALIZATION - Technologies are generally described for implementing non-linear VCSEL equalization. In some examples, a rising edge tap parameter, a falling edge tap parameter, an equalization delay and a bias current may be used to equalize a data signal to be output from a VCSEL. A VCSEL model may be used to derive a VCSEL response to one or more isolated data pulses. The derived response may then be used to determine the rising and falling edge tap parameters and an equalization delay, based on a bias current value for the VCSEL and a data rate associated with the data signal. The data signal may then be adjusted based on the equalization delay and the rising and falling edge tap parameter and sent to the VCSEL for output. At the same time, the VCSEL may be biased with a bias current having the bias current value. | 10-08-2015 |
Patent application number | Description | Published |
20080294609 | CANONICALIZATION OF TERMS IN A KEYWORD-BASED PRESENTATION SYSTEM - A presentation system accepts presentations or references to presentations from prospective presenters. Some or all of the presentations or references are stored in a database and referenced by keywords such that presentations to be presented in response to particular searches can be identified. A presentation manager handles accepting bids and settling terms between prospective presenters. The results of such processes might be stored in a presentation details database. A presentation server handles retrieving presentations from the presentation details database for presentation to users along with requests such as search results. Both the presentation manager and the presentation server can operate on a keywords-basis, wherein presentation terms specify keywords to be associated with particular presentations and the presentation server serves particular presentations based on keywords in a search query for which the presentations are to be returned. The association of keywords can be done using canonicalization so that, under certain conditions, different keywords are treated as the same keyword. Canonicalizations might include plural/singular forms, gender forms, stem word forms, suffix forms, prefix forms, typographical error forms, word order, pattern ignoring, acronyms, stop word elimination, etc. Conditions might include aspects of the search query state, such as the user's demographics, the page from which the search query was initiated, etc. | 11-27-2008 |
20140089130 | SYSTEM AND METHOD FOR MAKING GIFT RECOMMENDATIONS USING SOCIAL MEDIA DATA - Disclose are methods for evaluating a user's interests and making gift recommendations using social media data. Interests and attributes of a user may be detected from social media content and products corresponding to the interests and attributes may be selected and presented as gift recommendations for the user. Methods are disclosed for resolving ambiguity as to interests reflected by textual data in social media content. Also disclosed are methods for inferring a user's interests from the interests of friends of the user. | 03-27-2014 |
Patent application number | Description | Published |
20110191247 | AUTHENTICATION FRAMEWORK EXTENSION TO VERIFY IDENTIFICATION INFORMATION - Systems and methods for authenticating parties involved in a transaction are disclosed. Some embodiments of the disclosure are directed to systems and methods for authenticating various identification attributes of a participant in a transaction. The attributes can include items such as the participant's name, address, social security number, date of birth, or any other identifying attributes. In some embodiments, all participants in a transaction may have identification information authenticated. The 3-D Secure protocol and framework is extended and enhanced to provide the ability to authenticate the identification details of participants in transactions. | 08-04-2011 |
20110258111 | ALIAS MANAGEMENT AND OFF-US DDA PROCESSING - An alias management and off-us demand deposit account processing system is disclosed. A sending entity initiates a value transfer with a payment processing network indicating a value transfer providing issuer which will conduct the value transfer and a demand deposit account issuer which hosts the demand deposit account that funds the value transfer. The sending entity is able to conduct a value transfer via a value transfer providing issuer using funds from an account with another issuer. | 10-20-2011 |
20110258686 | Alias Management and Value Transfer Claim Processing - An alias management and value transfer claim processing system is disclosed. A sending entity initiates value transfer identifying a recipient entity using an alias that is unregistered with the system. The value transfer is authorized, but not settled until the recipient entity registers with the system and claims the value transfer. The registered alias can be used for subsequent value transfers. | 10-20-2011 |
20130179335 | ALIAS MANAGEMENT AND VALUE TRANSFER CLAIM PROCESSING - An alias management and value transfer claim processing system is disclosed. A sending entity initiates value transfer identifying a recipient entity using an alias that is unregistered with the system. The value transfer is authorized, but not settled until the recipient entity registers with the system and claims the value transfer. The registered alias can be used for subsequent value transfers. | 07-11-2013 |
20130218769 | Mobile Funding Method and System - Systems and methods for mobile funding are provided. One such method comprises receiving a transaction request to transfer funds from a payor to a payee. The transaction request can include a payor device identifier, a payee device identifier and an amount. A payor account identifier associated with the payor device identifier, and a payee account identifier associated with the payee device identifier can each be determined. Additionally, a first service provider associated with the payor device can be determined based on the payor device identifier, and a second service provider associated with the payee device can be determined based on the payee device identifier. The transfer of funds from the first service provider to the second service provider can then be initiated using the payor account identifier and the payee account identifier. At least one of the first and second service providers is a mobile network operator. | 08-22-2013 |
20130226799 | AUTHENTICATION PROCESS FOR VALUE TRANSFER MACHINE - Embodiments of the invention are directed towards improved transaction processing methods and systems with transaction apparatuses, including a value transfer machine, using a device identifier instead of a value transfer machine card to process a transaction. One embodiment of the transaction may be directed to a transaction apparatus and a method including receiving an authentication code from a consumer, sending the authentication code to a first server computer, wherein if the received authentication code matches a generated authentication code, the first server sends a confirmation message. The method continues by receiving the confirmation message from the first server, receiving a secret token from the consumer, and sending an authorization request message to a second server computer. Thereafter, the transaction apparatus receives an authorization response message from the second server, indicating whether the secret token matches an expected token. Other embodiments are directed to first and second servers and corresponding methods. | 08-29-2013 |
20130297501 | SYSTEM AND METHOD FOR LOCAL DATA CONVERSION - Embodiments of the invention are directed to methods, apparatuses, computer readable media and systems for processing transactions using conversion or filtering of restricted information. One embodiment of the invention is directed to a method comprising receiving, at a server computer located outside a restricted zone, a transaction request message including an unrestricted account alias, wherein the unrestricted account alias was previously converted from a restricted account identifier into the unrestricted account alias by a server computer located in a restricted zone. The server computer located outside the restricted zone may determine an account associated with the unrestricted account alias and process the transaction request message. Similar methods may be applied to settlement files including an unrestricted account alias that is converted to a restricted account identifier. Other embodiments are directed to filtering restricted information from service requests or other transactions. | 11-07-2013 |
20140344153 | MOBILE TOKENIZATION HUB - Embodiments of the present invention relate to systems and methods for implementing a mobile tokenization hub with a common tokenization capabilities (CTC) module that may provide tokenization for various entities in various contexts. For example, the CTC module can provide and store tokens for mobile payment transactions, transit transactions, digital wallet applications, merchant point of sale (POS) applications, personalization services, and the like. | 11-20-2014 |
20150161597 | TRANSACTIONS USING TEMPORARY CREDENTIAL DATA - A method is disclosed. The method includes receiving a credential request message requesting a temporary credential associated with a payment account, and then determining, by a server computer, using a routing table and data associated with the payment card, a third-party computer associated with the payment account. The method also includes transmitting the credential request message to the third-party computer, and receiving, by the server computer, the temporary credential from the third-party computer. The method also includes determining, by the server computer, the communication device associated with the requested temporary credential and transmitting, by the server computer, the temporary credential to the communication device. | 06-11-2015 |