Patent application number | Description | Published |
20090085122 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 04-02-2009 |
20090191792 | METHOD FOR CORROSION PREVENTION DURING PLANARIZATION - The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu | 07-30-2009 |
20090250818 | VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE - An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer. | 10-08-2009 |
20090294904 | INTEGRATED CIRCUIT SYSTEM EMPLOYING BACK END OF LINE VIA TECHNIQUES - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group. | 12-03-2009 |
20100001370 | INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace. | 01-07-2010 |
20100044869 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 02-25-2010 |
20100314763 | INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process. | 12-16-2010 |
20100314774 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 12-16-2010 |
20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 11-03-2011 |
20120168915 | RELIABLE INTERCONNECT INTEGRATION SCHEME - Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values. | 07-05-2012 |
20120255586 | APPARATUS AND METHODS FOR CLEANING AND DRYING OF WAFERS - An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates. | 10-11-2012 |
Patent application number | Description | Published |
20090302385 | HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER - An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region. | 12-10-2009 |
20100109097 | INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN - A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region. | 05-06-2010 |
20110042743 | LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates - First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region | 02-24-2011 |
20120119293 | HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER - An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region. | 05-17-2012 |
20130026565 | LOW RDSON RESISTANCE LDMOS - A device having a salicide block spacer on a second side of a gate is disclosed. The use of the salicide block spacer indirectly reduces the blocking effects during the implantation processes, thereby lowering the Rdson without compromising the breakdown voltage of the device. | 01-31-2013 |
20130062691 | SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE - A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer. | 03-14-2013 |
20130093012 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 04-18-2013 |
20130181286 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. | 07-18-2013 |
20130181287 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion. | 07-18-2013 |
20130320497 | ON-CHIP RESISTOR - An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor. | 12-05-2013 |
20140042499 | STRESS ENHANCED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench. | 02-13-2014 |
20140048874 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 02-20-2014 |
20140110783 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 04-24-2014 |
20140203325 | INTEGRATION OF GERMANIUM PHOTO DETECTOR IN CMOS PROCESSING - A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si. | 07-24-2014 |
20140264576 | INTEGRATION OF LOW RDSON LDMOS WITH HIGH SHEET RESISTANCE POLY RESISTOR - A method for forming a low Rds | 09-18-2014 |
20140264584 | LATERAL DOUBLE-DIFFUSED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction. | 09-18-2014 |
20140319607 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 10-30-2014 |
20140332884 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 11-13-2014 |
20150035067 | LOW RDSON DEVICE AND METHOD OF MANUFACTURING THE SAME - A device and method of making thereof are disclosed. The device includes a substrate having a device region for a switch transistor. The device includes a switch transistor having a gate disposed on the substrate in the device region and first and second heavily doped regions disposed adjacent to the gate. The first heavily doped region serves as a source region of the switch transistor and the second heavily doped region serves as a drain region of the switch transistor. The drain region includes a lightly doped diffusion (LDD) region adjacent thereto and the source region is devoid of a LDD region. | 02-05-2015 |
20150054076 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. | 02-26-2015 |
20150069522 | EFFICIENT INTEGRATION OF CMOS WITH POLY RESISTOR - Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion. | 03-12-2015 |
20150087132 | WAFER PROCESSING - Semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layer of the bottom pad stack is removed by a batch process. Trench isolation regions are formed in the substrate. | 03-26-2015 |
Patent application number | Description | Published |
20100145214 | SYSTEM AND METHOD FOR PROCESSING BRAIN SIGNALS IN A BCI SYSTEM - A system and method for processing brain signals in a BCI system. The method of processing brain signals in a BCI system includes the steps of processing the brain signals for control state detection to determine if a subject intends to use the BCI system; and processing the brain signals for command recognition if the control state detection method determines that the subject intends to use the BCI system. | 06-10-2010 |
20110191350 | METHOD AND SYSTEM FOR CONCENTRATION DETECTION - A method and system for concentration detection. The method for concentration detection comprises the steps of extracting temporal features from brain signals; classifying the extracted temporal features using a classifier to give a score x | 08-04-2011 |
20110289030 | METHOD AND SYSTEM FOR CLASSIFYING BRAIN SIGNALS IN A BCI - A method or system for classifying brain signals in a BCI. The system comprises a model building unit for building a subject-independent model using labelled brain signals from a pool of subjects. | 11-24-2011 |
20120108997 | DEVICE AND METHOD FOR GENERATING A REPRESENTATION OF A SUBJECT'S ATTENTION LEVEL - A device and method for generating a representation of a subject's attention level. The device comprises means for measuring brain signals from the subject; means for extracting temporal features from the brain signals; means for classifying the extracted temporal features using a classifier to give a score x | 05-03-2012 |
20120143104 | SYSTEM AND METHOD FOR MOTOR LEARNING - A method and system for motor learning. The method comprises the steps of detecting a user's motor intent; and giving robotic assistance to the user for executing a motor task associated with the motor intent based on the detected motor intent. | 06-07-2012 |
20130138011 | BRAIN-COMPUTER INTERFACE SYSTEM AND METHOD - A system and method for brain-computer interface (BCI) based interaction. The method comprising the steps of: acquiring a person's EEG signal; processing the EEG signal to determine a motor imagery of the person; detecting a movement of the person using a detection device; and providing feedback to the person based on the motor imagery, the movement, or both; wherein providing the feedback comprises activating a stimulation element of the detection device for providing a stimulus to the person. The system comprising: means for acquiring a person's EEG signal; means for processing the EEG signal to determine a motor imagery of the person; means for detecting a movement of the person using a detection device; and means for providing feedback to the person based on the motor imagery, the movement, or both; wherein the means for providing the feedback comprises a stimulation element of the detection device for providing a stimulus to the person. | 05-30-2013 |
20130331727 | METHOD AND SYSTEM FOR DETECTING ATTENTION - A method and system for detecting attention of a subject is provided. The method comprises determining one or more user specific feature sets from Electroencephalographic (EEG) signals of the subject; determining one or more pool data feature sets from the EEG signals of the subject; identifying one or more features from each feature set for differentiating attention/non-attention signals; determining respective classification scores for each feature set based on the identified one or more features; and combining the classification scores to obtain a combined attention score for said detecting attention. | 12-12-2013 |
20140018694 | METHOD AND SYSTEM FOR MOTOR REHABILITATION - A method of calibrating a motor imagery detection module and a system for motor rehabilitation are provided. The method comprises acquiring Electroencephalography (EEG) data from a subject; selecting classification features from the EEG data; wherein the feature selection comprises modelling an idle state ω | 01-16-2014 |
20150073294 | METHOD FOR ASSESSING THE TREATMENT OF ATTENTION-DEFICIT/HYPERACTIVITY DISORDER - According to one aspect, there is provided a method for assessing the treatment of attention-deficit/hyperactivity disorder (ADHD) in a subject, the method comprising: obtaining electroencephalographic (EEG) data relating to a plurality of subjects diagnosed with ADHD; extracting, for each of the plurality of subjects, at least one feature from the EEG data relating to that subject; formulating a prediction model by performing regression analysis to map the extracted features against one or more markers for each of the plurality of subjects; and determining that the prediction model provides an ADHD assessment if one or more of the markers are indicators of a clinical measure of interest. | 03-12-2015 |
Patent application number | Description | Published |
20120019305 | HARMONIC REJECTION OF SIGNAL CONVERTING DEVICE AND METHOD THEREOF - A signal converting device includes: a reference signal-mixing circuit arranged to generate a reference mixing output signal according to an input signal, a reference gain, and a reference local oscillating signal; a plurality of auxiliary signal-mixing circuits, each arranged to generate an auxiliary mixing output signal according to the input signal, an auxiliary gain, and an auxiliary local oscillating signal; and a combining circuit arranged to combine the reference mixing output signal and a plurality of the auxiliary mixing output signals to generate an output signal, and at least one of the auxiliary signal-mixing circuits is configured by the corresponding auxiliary gain to compensate phase imbalances between the reference mixing output signal and each of the auxiliary mixing output signals to reduce a power of a harmonic component in the output signal. | 01-26-2012 |
20140104005 | VOLTAGE-TO-CURRENT CONVERTER AND VOLTAGE CONTROLLED OSCILLATOR HAVING VOLTAGE-TO-CURRENT CONVERTER - A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current. | 04-17-2014 |
20140218080 | METHOD AND SYSTEM FOR FAST SYNCHRONIZED DYNAMIC SWITCHING OF A RECONFIGURABLE PHASE LOCKED LOOP (PLL) FOR NEAR FIELD COMMUNICATIONS (NFC) PEER TO PEER (P2P) ACTIVE COMMUNICATIONS - A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock. | 08-07-2014 |
Patent application number | Description | Published |
20140032731 | Recursive, All-to-All Network Topologies - An apparatus comprises an interconnection network comprising N | 01-30-2014 |
20140032853 | Method for Peer to Peer Cache Forwarding - A home node for selecting a source node using a cache coherency protocol, comprising a logic unit cluster coupled to a directory, wherein the logic unit cluster is configured to receive a request for data from a requesting cache node, determine a plurality of nodes that hold a copy of the requested data using the directory, select one of the nodes using one or more selection parameters as the source node, and transmit a message to the source node to determine whether the source node stores a copy of the requested data, wherein the source node forwards the requested data to the requesting cache node when the requested data is found within the source node, and wherein some of the nodes are marked as a Shared state corresponding to the cache coherency protocol. | 01-30-2014 |
20140032854 | Coherence Management Using a Coherent Domain Table - A computer program product comprising computer executable instructions stored on a non-transitory medium that when executed by a processor cause the processor to perform the following: assign a first, second, third, and fourth coherence domain address to a cache data, wherein the first and second address provides the boundary for a first coherence domain, and wherein the third and fourth address provides the boundary for a second coherence domain, inform a first resource about the first coherence domain prior to the first resource executing a first task, and inform a second resource about the second coherence domain prior to the second resource executing a second task. | 01-30-2014 |
20140033209 | Handling of Barrier Commands for Computing Systems - A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification messages from the target computing system. The pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed. The processor is coupled to the interface and is configured to determine a status of the barrier command based on the received barrier completion notification messages. | 01-30-2014 |
20140036680 | Method to Allocate Packet Buffers in a Packet Transferring System - A method comprising receiving a credit status from a second node comprising a plurality of credits used to manage the plurality of allocations of storage space in a buffer of the second node, wherein each of the plurality of allocations are dedicated to a different packet type, instructing the second node to use the credit dedicated to a second priority packet type for storing a first priority packet type, wherein the first priority is higher than the second priority, and wherein the credit status reflects the credits for the first priority packet type having reached a minimum value, and transmitting the first priority packet to the second node. | 02-06-2014 |
20140036919 | Forward Progress Assurance and Quality of Service Enhancement in a Packet Transferring System - A method comprising detecting at least one Quality of Service (QoS) requirement is met that indicates a very important packet (VIP) is outstanding from a source node in a multi-hop network comprising multiple nodes, sending an initiation message to an adjacent node in response to the detection that may activate a protocol in which a reserved channel is activated, and receiving the VIP via the reserved channel. Also, a method comprising receiving an initiation message from an adjacent node in a multi-hop network that comprises information identifying the VIP comprising a source node, a destination node, a packet type, wherein the initiation message activates a protocol in which a reserved channel is activated, searching for the VIP identified by the initiation message, and forwarding the VIP promptly if present via the reserved channel or forwarding an initiation message to adjacent nodes closer to the source node. | 02-06-2014 |
20140036929 | Phase-Based Packet Prioritization - A network node comprises a receiver configured to receive a first packet, a processor coupled to the receiver and configured to process the first packet, and prioritize the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and a transmitter coupled to the processor and configured to transmit the first packet. An apparatus comprises a processor coupled to the memory and configured to generate instructions for a packet prioritization scheme, wherein the scheme assigns priority to packet transactions based on closeness to completion, and a memory coupled to the processor and configured to store the instructions. A method comprises receiving a first packet, processing the first packet, prioritizing the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and transmitting the first packet. | 02-06-2014 |
20140036930 | Priority Driven Channel Allocation for Packet Transferring - A method comprising advertising to a second node a total allocation of storage space of a buffer, wherein the total allocation is less than the capacity of the buffer, wherein the total allocation is partitioned into a plurality of allocations, wherein each of the plurality of allocations is advertised as being dedicated to a different packet type, and wherein a credit status for each packet type is used to manage the plurality of allocations, receiving a packet of a first packet type from the second node, and storing the packet to the buffer, wherein the space in the buffer occupied by the first packet type exceeds the advertised space for the first packet type due to the packet. | 02-06-2014 |
20140040561 | HANDLING CACHE WRITE-BACK AND CACHE EVICTION FOR CACHE COHERENCE - A method implemented by a computer system comprising a first memory agent and a second memory agent coupled to the first memory agent, wherein the second memory agent has access to a cache comprising a cache line, the method comprising changing a state of the cache line by the second memory agent, and sending a non-snoop message from the second memory agent to the first memory agent via a communication channel assigned to snoop responses, wherein the non-snoop message informs the first memory agent of the state change of the cache line. | 02-06-2014 |
20140052905 | Cache Coherent Handshake Protocol for In-Order and Out-of-Order Networks - Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver. | 02-20-2014 |
20140052916 | Reduced Scalable Cache Directory - A processing network comprising a cache configured to store copies of memory data as a plurality of cache lines, a cache controller configured to receive data requests from a plurality of cache agents, and designate at least one of the cache agents as an owner of a first of the cache lines, and a directory configured to store cache ownership designations of the first cache line, and wherein the directory is encoded to support substantially simultaneous ownership of the first cache line by a plurality but less than all of the cache agents. Also disclosed is a method comprising receiving coherent transactions from a plurality of cache agents, and storing ownership designations of a plurality of cache lines by the cache agents in a directory, wherein the directory is configured to support storage of substantially simultaneous ownership designations for a plurality but less than all of the cache agents. | 02-20-2014 |
Patent application number | Description | Published |
20090146258 | SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS - A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction. | 06-11-2009 |
20120007214 | INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor. | 01-12-2012 |
20140210009 | HIGH VOLTAGE FINFET STRUCTURE - Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region. | 07-31-2014 |
20140332887 | SILICON-ON-INSULATOR INTEGRATED CIRCUITS WITH LOCAL OXIDATION OF SILICON AND METHODS FOR FABRICATING THE SAME - Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor that includes source and drain regions located in the semiconductor substrate, a gate dielectric layer located between the source and drain regions, and a local oxide layer located in a second portion of the semiconductor substrate and extending a second depth below the upper surface of the semiconductor substrate. The first depth is greater than the second depth. Still further, the integrated circuit includes a first gate electrode that extends over the gate dielectric layer and the local oxide layer. | 11-13-2014 |
20150028407 | 3D HIGH VOLTAGE CHARGE PUMP - A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second. C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics. The C3 includes a first C3 plate served by the gate electrode, a second C3 plate served by second group lines in the first metal level of the ILD layers, and a C3 capacitor dielectric is served by the first via level dielectric below M1 and above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C1, C2 and C3 and a second capacitor terminal is coupled to second capacitor plates of C1, C2 and C3. | 01-29-2015 |
Patent application number | Description | Published |
20100148507 | METHOD FOR CONTROLLING THE OPERATION OF A WIND TURBINE AND A WIND TURBINE - A method for controlling the operation of a wind turbine includes determining a first measure of a mechanical input of a component of the wind turbine, and concurrently, determining a second measure of a mechanical output of the component, determining an operating frequency response function of the component from an analysis of the relation between the first measure and the second measure, comparing the operating frequency response function with a predetermined operating frequency response function and determining a possible deviation between the two, and controlling the operation of the wind turbine so as to alter the mechanical input to the component in response to the deviation. A wind turbine that implements such a method is also disclosed. | 06-17-2010 |
20100298995 | METHOD AND SYSTEM FOR CONTROLLING OPERATION OF A WIND TURBINE - Methods and systems for controlling operation of a wind turbine. The method may comprise determining an alarm level for at least one component of the wind turbine. In the case that an alarm level for at least one component exceeds a predefined level, the method comprises estimating an expected remaining lifetime for the component under the current operating conditions, and controlling operation of the wind turbine in order to adjust the expected remaining lifetime for the component to a desired expected remaining lifetime for said component. Thereby, the expected remaining lifetime for the component can be prolonged until the next scheduled service event. Downtime of the wind turbine is considerably reduced, and unscheduled service events are avoided to the greatest possible extent. Mean time between inspections (MTBI) is also extended. | 11-25-2010 |
20100332272 | Method and a system for controlling operation of a wind turbine - A method and a system for controlling operation of a wind turbine are provided. The method includes determining at least one failure mode relating to one or more components of the wind turbine, estimating a remaining lifetime of the component under current operating conditions, determining one or more control schemes to control the operation of the wind turbine in order to adjust the remaining lifetime of the component to a desired remaining lifetime of the component, determining a power production yield for the determined one or more control schemes and selecting a determined control scheme for controlling the operation of the wind turbine that maximizes the power production yield. | 12-30-2010 |
20110052368 | METHOD AND A SYSTEM FOR ADJUSTING ALARM LEVEL OF A COMPONENT IN A WIND TURBINE - A method and a system for adjusting alarm level of a component in a wind turbine is provided. The method comprises defining an alarm level corresponding to an operational parameter of the component in the wind turbine, monitoring the operational parameter of the component, determining whether the operational parameter exceeds the alarm level, thereby triggering an alarm. In the case when the alarm is triggered, the method further comprises inspecting the component to determine whether the alarm level corresponds to a predetermined remaining useful lifetime of the component, and adjusting the alarm level based on the inspection of the component. | 03-03-2011 |
Patent application number | Description | Published |
20100052064 | METHOD FOR STRAINING A SEMICONDUCTOR WAFER AND A WAFER SUBSTRATE UNIT USED THEREIN - The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit. | 03-04-2010 |
20110129910 | COOLING DEVICE, AND ASSEMBLY, AND METHODS FOR LOWERING TEMPERATURE IN A CHEMICAL REACTION - Embodiments provide a cooling device. The cooling device comprises a container configured as a heat sink. The container is at least partially made from heat conducting material. The cooling device further comprises endothermic chemical material which is contained in the container. | 06-02-2011 |
20120119390 | SEMICONDUCTOR STRUCTURE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided. | 05-17-2012 |
20130199303 | Bonding Stress Testing Arrangement and Method of Determining Stress - A bonding stress testing arrangement and a method of determining stress are provided. The bonding stress testing arrangement includes at least one bond pad; a sensor assembly comprising any one of a first sensor arrangement, a second sensor arrangement and a combination of the first sensor arrangement and the second sensor arrangement; wherein the first sensor arrangement is adapted to measure an average stress on a portion of a bonding area under the at least one bond pad, and the second sensor arrangement is adapted to determine stress distribution over a portion or an entire of the bonding area under the at least one bond pad. | 08-08-2013 |
20130328209 | Stack Arrangement - In an embodiment, a stack arrangement is provided. The stack arrangement may include a semiconductor arrangement, the semiconductor arrangement including a substrate; a via formed through the substrate; and a conductive portion arranged in the via. The stack arrangement may further include an interconnect portion arranged over the via; a bond pad portion arranged between the semiconductor arrangement and the interconnect portion, the bond pad portion may include a bond pad circumferential portion arranged at least partially circumferential with respect to the via and at a first distance away from the conductive portion; and at least one bond pad electrical connection extending from within the bond pad circumferential portion to the conductive portion; wherein the interconnect portion may be arranged away from the conductive portion via the bond pad portion. | 12-12-2013 |
Patent application number | Description | Published |
20100013081 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 01-21-2010 |
20100109169 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly. | 05-06-2010 |
20100261313 | SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate. | 10-14-2010 |
20130119560 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 05-16-2013 |
Patent application number | Description | Published |
20080316112 | Antennas - An antenna on a substrate, the antenna being symmetrical about a central longitudinal axis of symmetry, the antenna comprising a first portion that is substantially rectangular, a second portion that is substantially rectangular, the first portion and the second portion being spaced from each other and being operatively connected by an intermediate portion. | 12-25-2008 |
20090236701 | Chip arrangement and a method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement - A chip arrangement is disclosed. The chip arrangement includes a first chip, a first bond wire having an inductive element and coupled with the first chip at its one end and an inductivity compensation structure including a first conductive plate coupled with the first bond wire at the other end of the first bond wire, and a second conductive plate arranged in parallel to the first conductive plate, wherein the first conductive plate and the second conductive plate are configured such that a resonant condition for a partial circuit formed by the first bond wire and the inductivity compensation structure is formed to compensate for the inductive element of the first bond wire. A method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement is also disclosed. | 09-24-2009 |
20100001351 | TRIPLE WELL TRANSMIT-RECEIVE SWITCH TRANSISTOR - A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor. | 01-07-2010 |
20100219513 | INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FORMING THE SAME - An integrated circuit structure is disclosed. The integrated circuit structure includes a first package substrate including a radiating element, the radiating element having a radiating element connection extending from the radiating element. The integrated circuit structure further includes a first chip positioned adjacent to the radiating element connection, the first chip having a first chip connection on a surface of the first chip, wherein the first chip connection forms a capacitive coupling with the radiating element connection. A method of forming an integrated circuit structure is also disclosed. | 09-02-2010 |
20100237946 | Low Noise Amplifier Circuit with Noise Cancellation and Increased Gain - A low noise amplifier circuit including a front end voltage sensing and matching amplification circuit, a gain circuit and a combining circuit is disclosed. The front end voltage sensing and matching amplification circuit includes an input and two outputs and provides a matched signal at each output. The gain circuit includes two inputs, each input being respectively coupled to at least one of the two outputs of the front end voltage sensing and matching amplification circuit. The gain circuit further includes two outputs and an output signal is provided at each output of the gain circuit. The combining circuit combines the two output signals of the gain circuit. The combining circuit includes two inputs, each input is respectively coupled to at least one of the two outputs of the gain circuit. The combining circuit further includes an output providing a combined signal. | 09-23-2010 |
20110241969 | GRID ARRAY ANTENNAS AND AN INTEGRATION STRUCTURE - A grid array antenna configured to operate with millimetre wavelength signals, the grid array antenna comprising a plurality of mesh elements and at least one radiation element; each mesh element comprising at least one long side and at least one short side operatively connected to the at least one long side; at least one of: the at least one radiating element, the at least one short side, and the at least one long side having compensation for improved antenna output for improved antenna radiation. | 10-06-2011 |
20140327495 | SPST SWITCH, SPDT SWITCH, SPMT SWITCH AND COMMUNICATION DEVICE USING THE SAME - Various embodiments provide a single pole single throw switch. The switch may include a first terminal, a second terminal and a control terminal; a field-effect transistor having a drain connected to the first terminal, a source connected to the ground, and a gate; a bias resistor connected between the gate of the field-effect transistor and the control terminal; an inductor connected between the first terminal and the second terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground. | 11-06-2014 |
20150054594 | SWITCH - A switch for controlling signal propagation between a first and second contact is proposed. This switch comprises a control mechanism configured to allow signal propagation between the first and second contacts when the switch is turned on and prevent signal propagation between the first and second contacts when the switch is turned off. The switch also comprises a compensating member having a transmission line and a ground plane. The ground plane in turn comprises at least one defect configured to affect one or both of the inductance and capacitance of the transmission line when signals propagate through the transmission line. | 02-26-2015 |