Liang, NY
Benjamin Liang, East Setauket, NY US
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20150104800 | SYSTEM AND METHOD FOR MARKING TEXTILES WITH NUCLEIC ACIDS - A method for authenticating a textile material that is initiated by selecting a unique nucleic acid marker having a specific length and a specific sequence. A media that causes the unique nucleic acid marker to adhere to a fibrous material is then selected. The method then proceeds to generate a nucleic acid marker mixture by mixing the media with the nucleic acid marker. The nucleic acid marker mixture is then applied to the fibrous material. A marked fibrous material is produced by marking the fibrous material with the nucleic acid marker. The textile material is manufactured with the marked fibrous material. The textile material is then authenticated by detecting the unique nucleic acid marker with primers that are specific to the unique nucleic acid. | 04-16-2015 |
Benjamin Minghwa Liang, East Setauket, NY US
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20130149706 | OPTICAL REPORTER COMPOSITIONS - This invention provides compositions that have a light emitting reporter linked to biomolecules, preferably, nucleotide oligomers. The light reporter particles are silylated and functionalized to produce a coated light reporter particle, prior to covalently linking the biomolecules to the light reporter particle. The light reporter particles of the invention can be excited by a light excitation source such as UV or IR light, and when the biomolecule is DNA, the attached DNA molecule(s) are detectable by amplification techniques such as PCR. | 06-13-2013 |
20160076088 | LASER MARKING FOR AUTHENTICATION AND TRACKING - Methods for incorporating and/or immobilizing security markers by exposure to an electromagnetic pulse, such as for instance a LASER pulse, to produce a marked object that can be authenticated only by using proprietary biological, chemical or physical analysis, the method includes: exposing a surface of the object to be marked to an electromagnetic pulse to activate the surface or a coating on the surface, and exposing the surface to a detectable marker molecule and thereby immobilizing the detectable marker molecule, such as a biological marker molecule, e.g. DNA on the surface of the object. The method of marking the object may include exposing a photo-polymerizable monomer on at least a portion of the surface of an object to be marked to a LASER pulse to initiate a reaction to cross link the photo-polymerizable monomer binding, trapping or encapsulating a detectable marker on the surface of the object. | 03-17-2016 |
Chao Liang, Brooklyn, NY US
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20100042668 | HIERARCHICALLY CLUSTERED P2P STREAMING SYSTEM - A HCPS (hierarchically clustered P2P streaming system) comprising peers grouped into clusters and hierarchies. The HCPS actively balances the uploading capabilities among clusters and executes an optimal scheduling algorithm within each cluster to ensure that system resources are optimally utilized. The HCPS comprises an architecture which can be used in practical applications, yet can achieve the streaming rate close to the theoretical upper bound. | 02-18-2010 |
20100138511 | QUEUE-BASED ADAPTIVE CHUNK SCHEDULING FOR PEER-TO PEER LIVE STREAMING - A method and apparatus are described for scheduling content delivery in a peer-to-peer network, including receiving a message from a peer, classifying the received message, storing the classified message in one of a plurality of queues based on the classification, generating responses to messages based on a priority of the queue in which the classified message is stored and transmitting content to all peers in the peer-to-peer network. Also described are a method and apparatus for scheduling content delivery in a peer-to-peer network, including receiving one of a message and content from one of a content source server and a peer, classifying the received message, storing the classified message in one of a plurality of queues based on the classification, storing the received content, generating responses to messages based on a priority of the queue in which the classified message is stored and transmitting content to all other peers in the peer-to-peer network. | 06-03-2010 |
20110047215 | DECENTRALIZED HIERARCHICALLY CLUSTERED PEER-TO-PEER LIVE STREAMING SYSTEM - A method and apparatus are described including forwarding data in a transmission queue to a first peer in a same cluster, computing an average transmission queue size to a threshold, sending a signal to a cluster head based on a result of the comparison. A method and apparatus are also described including forwarding data in a transmission queue to a peer associated with an upper level peer, forwarding data in a playback buffer to a peer in a lower level cluster responsive to a first signal in a signal queue associated with the lower level cluster, determining if the playback buffer has exceeded a threshold for a period of time, sending a second signal to a source server based on a result of the determination. | 02-24-2011 |
20110173265 | MULTI-HEAD HIERARCHICALLY CLUSTERED PEER-TO-PEER LIVE STREAMING SYSTEM - A method and apparatus are described including receiving data from a plurality of cluster heads and forwarding the data to peers. Also described are a method and apparatus including calculating a sub-stream rate, splitting data into a plurality of data sub-streams and pushing the plurality of data sub-streams into corresponding transmission queues. Further described are a method and apparatus including splitting source data into a plurality of equal rate data sub-streams, storing the equal rate data sub-streams into a sub-server content buffer, splitting buffered data into a plurality of data sub-streams, calculating a plurality of sub-stream rates and pushing the data sub-streams into corresponding transmission queues. | 07-14-2011 |
Chu-Hsin Liang, Lake Carmel, NY US
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20090189195 | Radio Frequency (RF) Circuit Placement in Semiconductor Devices - Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices. | 07-30-2009 |
Dawen Liang, New York, NY US
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20150142450 | Sound Processing using a Product-of-Filters Model - Sound processing using a product-of-filters model is described. In one or more implementations, a model is formed by one or more computing devices for a time frame of sound data as a product of filters. The model is utilized by the one or more computing devices to perform one or more sound processing techniques on the time frame of the sound data. | 05-21-2015 |
Desmond Liang, New York, NY US
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20090119194 | SYSTEM AND METHOD FOR FACILITATING A SECURED FINANCIAL TRANSACTION USING AN ALTERNATE SHIPPING ADDRESS - The disclosed system enables merchants to ship products to a predefined address that may or may not be an account holder's billing address. The account holder may define one or more alias identifiers that correspond to a predefined shipping address. The predefined shipping address is stored with a corresponding alias identifier. A merchant order form includes a field to accept an alias identifier, such that when the order form is submitted to the merchant and the merchant prepares a purchase authorization request, the alias identifier is included in the request. The credit account issuer receives the payment authorization request and extracts the alias identifier, which is used to locate a matching stored alias identifier. A shipping address corresponding to the stored alias identifier is retrieved and returned to the merchant with an authorization message. | 05-07-2009 |
Erwin W. Liang, Ballston Lake, NY US
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20090067155 | METHOD AND APPARATUS FOR FABRICATING OPTICAL SUBSTRATES - In one embodiment, an optical substrate that includes a prism structure modulated along a path in a lateral direction. The path is in the nature of a mathematical function defined over a segment, C, of a coordinate system and characterized by a set of nonrandom, random or pseudorandom parameters selected from the group consisting of amplitude, phase and frequency. | 03-12-2009 |
Frank Ting Liang, Poughkeepsie, NY US
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20090313181 | SYSTEM AND METHOD FOR INTERNATIONAL PARTNER COLLABORATION - A system and associated method for gathering data necessary for exchanging a product between at least two partners. Each partner in said at least two partners resides in a different country. The method provides for gathering information regarding the product being exchanged and more specifically a delivery location, a returning date and returning location if the product is being returned to said sending partner, a single valuation for said product being exchanged, a lot number for said product, clean-room requirements for said receiving partners, a product history, and a genealogy of said product being exchanged. After collecting the information, the method formats said information according to the specific receiving partner's requirements. The method further determines the appropriate method of transmission according to each receiving partner's requirements. Finally, the method sends each receiving partner their specifically formatted version of the information regarding the product being exchanged. | 12-17-2009 |
Guang Liang, Elmhurst, NY US
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20090232448 | Fiber optic multiplexer - A fiber optic multiplexer comprises a stationary frame to which primary and secondary optical fibers are attached, a rotary frame to which both ends of a transfer optical fiber are attached, and a means of rotating the rotary frame through a predetermined angle relative to the stationary frame. The primary end of the transfer optical fiber is coaxial with the primary optical fiber and the rotary frame axis of rotation. The secondary end of the transfer optical fiber is initially coaxial with a first secondary optical fiber. The multiplexer is switched by rotating the rotary frame through the predetermined angle to coaxially align the secondary end of the transfer optical fiber with a second secondary optical fiber. | 09-17-2009 |
20140206090 | ETCHANT PRODUCT ANALYSIS IN ALKALINE ETCHANT SOLUTIONS - Silicon ions in an alkaline etchant solution are analyzed by acidifying a sample of the etchant solution, adding fluoride ions in excess of the concentration required to react with all of the silicon ions, and using a fluoride ion specific electrode (FISE) to detect free fluoride ions in the resulting test solution. Good sensitivity and precision are provided by using a relatively acidic test solution and only a slight excess of fluoride ions, and limiting the analysis range to the maximum expected silicon concentration in the etchant solution. | 07-24-2014 |
Hongying Liang, Bronx, NY US
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20120028795 | Methods For Producing Nanoparticles Using Palladium Salt And Uses Thereof - The disclosed subject matter is directed to a method for producing nanoparticles, as well as the nanoparticles produced by this method. In one embodiment, the nanoparticles produced by the disclosed method have a high defect density. | 02-02-2012 |
Jason Liang, Fresh Meadows, NY US
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20100263217 | Food mincer with retractable blade cover - A food mincer assembly comprises a handle assembly, a retractable blade cover, and a plurality of blades. The handle assembly has a first side and a second side. The first side has a first through hole and the second side has a second through hole. The retractable blade cover has a cover portion, a lock, and a connecting arm. The connecting arm attaches the blade cover to the handle assembly. The lock secures the blade cover in a first position or a second position. The plurality of blades attach to the handle assembly. The first position of the retractable blade cover covers the plurality of blades. The second position of the retractable blade cover exposes the plurality of blades. | 10-21-2010 |
20110100164 | Self-Pulling Corkscrew - A self-pulling corkscrew is provided. The corkscrew includes a body comprised of a first arm extending downwardly from a central portion and a second arm extending downwardly from the central portion. The first and second arms each having an inner surface and an outer surface wherein the inner surfaces of the first arm and the second arm cooperatively define a bottle receiving cavity. The corkscrew further includes a first groove traversing at least a portion of the outer surface of the first arm and a second groove traversing at least a portion of the outer surface of the second arm. One of either the first and second grooves has a first depth at a proximate end of the groove and a second depth at a distal end of the groove. The corkscrew is further comprised of a sleeve, a handgrip and a screw. The sleeve is slidably engaged with the first and second arms and has a first inwardly projecting protrusion and a second inwardly projecting protrusion. The first protrusion cooperatively engages the first groove and the second protrusion cooperatively engages the second groove. The handgrip is attached to the body proximate the central portion, and the screw is coupled to the handgrip. The screw extends into the bottle receiving cavity between the inner surfaces of the first and second arms. | 05-05-2011 |
Jermoe Z. Liang, Stony Brook, NY US
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20100260390 | SYSTEM AND METHOD FOR REDUCTION OF FALSE POSITIVES DURING COMPUTER AIDED POLYP DETECTION - A computer aided detection (CAD) method for detecting polyps within an identified mucosa layer of a virtual representation of a colon includes the steps of identifying candidate polyp patches in the surface of the mucosa layer and extracting the volume of each of the candidate polyp patches. The extracted volume of the candidate polyp patches can be partitioned to extract a plurality of features, of the candidate polyp patch, which includes at least one internal feature of the candidate polyp patch. The features can include density texture features, geometrical features, and morphological features of the polyp candidate volume. The extracted features of the polyp candidates are analyzed to eliminate false positives from the candidate polyp patches. Those candidates which are not eliminated are identified as polyps. | 10-14-2010 |
Jerome Liang, Stony Brook, NY US
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20080281181 | Combination of Multi-Modality Imaging Technologies - Different applications for multiple imaging technologies are provided to advance patient care. In one aspect, a 3-D imaging device is used to identify the location of target region in a patient, such as a tumor or aneurysm, for instance. The location information is then used to control a device used in performing a surgical or other intervention, further imaging or a diagnostic or therapeutic procedure ( | 11-13-2008 |
Jerome Z. Liang, Stony Brook, NY US
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20100208956 | ELECTRONIC COLON CLEANSING METHOD FOR VIRTUAL COLONOSCOPY - A method for electronically cleansing a virtual object formed from acquired image data converted to a plurality of volume elements is provided. The present method allows individual volume elements, or voxels, to represent more than one material type. The method includes defining a partial volume image model for volume elements representing a plurality of material types based, at least in part, on the measured intensity value of the volume element. The material mixture for each of the volume elements representing a plurality of material types can be estimated using the observed intensity values and the defined partial volume image model. The volume elements representing a plurality of material types can then be classified in accordance with the estimated material mixture. For electronic colon cleansing, the method includes removing at least one classification of volume elements when displaying the virtual object. | 08-19-2010 |
20100266178 | SYSTEM AND METHOD FOR ACCELERATION OF IMAGE RECONSTRUCTION - A method for reconstructing an image from emission data includes generating a compressed point-spread function matrix, generating an accumulated attenuation factor; and performing at least one image projection operation on an image matrix of the emission data using the compressed point-spread function matrix and the accumulated attenuation factor. The image projection operation can include rotating an image matrix and an exponential attenuation map to align with a selected viewing angle. An accumulated attenuation image is then generated from the rotated image matrix and rotated exponential attenuation map and a projection image is generated for each voxel by multiplying the accumulated attenuation image and point spread function matrix for each voxel. The rotating and multiplying operations can be performed on a graphics processing unit, which may be found in a commercially available video processing card, which are specifically designed to efficiently perform such operations. | 10-21-2010 |
20160055658 | ITERATIVE RECONSTRUCTION FOR X-RAY COMPUTED TOMOGRAPHY USING PRIOR-IMAGE INDUCED NONLOCAL REGULARIZATION - Disclosed is a method for performing X-ray Computed Tomography scanning, the method including acquiring a plurality of images of an object, obtaining an initial image from the plurality of images, calculating NonLocal weight of the initial image, utilizing a current image estimation and registered prior image, performing a successive over-relaxation optimization to yield a new image estimation with an intensity of the new image estimation equal or greater than zero, performing a cycle update, generating an image of the object utilizing the new image estimation obtained from the optimization, and outputting a resultant image. | 02-25-2016 |
Jerome Zheng Liang, Stony Brook, NY US
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20150065868 | SYSTEM, METHOD, AND COMPUTER ACCESSIBLE MEDIUM FOR VOLUMETRIC TEXTURE ANALYSIS FOR COMPUTER AIDED DETECTION AND DIAGNOSIS OF POLYPS - A computer-based method for diagnosing a region of interest within an anatomical structure having the steps of receiving a 3D volumetric representation of the anatomical structure, and identifying at least one volume of interest and volume of normal of the anatomical structure. A first feature set can be generated based on a density, a gradient and a curvature of the volume of interest, and the first feature set can be compared to a second feature set to diagnose the region of interest to at least one a plurality of pathology types. | 03-05-2015 |
20150379709 | METHOD FOR ADAPTIVE COMPUTER-AIDED DETECTION OF PULMONARY NODULES IN THORACIC COMPUTED TOMOGRAPHY IMAGES USING HIERARCHICAL VECTOR QUANTIZATION AND APPARATUS FOR SAME - Provided are an apparatus and method for fast and adaptive computer-aided detection of pulmonary nodules and differentiation of malignancy from benignancy in thoracic CT images using a hierarchical vector quantization scheme. Anomalous pulmonary nodules are detected by obtaining a two-dimensional (2D) feature model of a pulmonary nodule, segmenting the pulmonary nodule by performing vector quantification to expand the 2D feature model to a three-dimensional (3D) model, and displaying image information representing whether the pulmonary nodule is benign, based upon the 3D model expanded from the 2D feature model, with duplicate information eliminated by performing feature reduction performed using a principal component analysis and a receiver operating characteristics area under the curve merit analysis. A textural feature analysis detects an anomalous pulmonary nodule, and 2D texture features are calculated from 3D volumetric data to provide improved gain compared to calculation from a single slice of 3D data. | 12-31-2015 |
Jerome Zhengrong Liang, Stony Brook, NY US
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20160066856 | MAGNETIC RESONANCE IMAGING METHOD - Provided is a method for compensating for tissue motion during magnetic resonance (MR) imaging, and an apparatus for use thereof. The method includes acquiring a plurality of short-time MR scan images; selecting a reference scan image from the acquired plurality of short-time MR scan images; defining a set of transformation images based on the acquired plurality of short-time MR scan images other than the selected reference scan image; registering the reference scan image and the defined set of transformation images; calculating an average of aligned, registered images of the defined set of transformation images; and generating a motion-corrected image based on the calculated average. | 03-10-2016 |
Jian Liang, Huntington Station, NY US
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20080313241 | DISTRIBUTED DATA STORAGE USING ERASURE RESILIENT CODING - An erasure resilient coding (ERC) distributed data storage system and method for storing data in a reliable and survivable fashion while minimizing hardware and associated costs. The system and method includes forming multiple protection groups both within and across storage nodes of the storage system. Data is segmented into original data blocks and ERC data blocks. Load balancing occurs by interleaving storage nodes with equal numbers of original data blocks and ERC data blocks while ensuring each node has an equal number of combined read and write operations. Unique read and write operations on data block can be performed independent of other data blocks in a protection group. The write operation uses Galois field arithmetic and ERC transform to either write or append a new data block to a storage node. The read operation recovers data in a variety of ways using ERC decoding. | 12-18-2008 |
Jian Wen Liang, Brooklyn, NY US
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20120168338 | FOOD CONTAINER - This invention is directed to a food container comprising a lid and a base. The lid and base form three seals, including a locking seal, to prevent the leakage or spoilage of food during transport or temporary storage. Blades on the lid sealing edge and blades on the base sealing edge strengthen said edges, and further reinforce the seals formed between the lid and base. The lid and base, separately or when assembled, are stably stackable requiring a minimal amount of storage space. | 07-05-2012 |
Jim Shih-Chun Liang, Poughkeepsie, NY US
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20150279733 | HARDMASK REMOVAL FOR COPPER INTERCONNECTS WITH TUNGSTEN CONTACTS BY CHEMICAL MECHANICAL POLISHING - The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench. | 10-01-2015 |
Jing Liang, Brooklyn, NY US
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20130185839 | LEG GUARD ASSEMBLY - A leg guard assembly comprises an elongated pad extending along the outside of the leg guard assembly, a shin guard sleeve positioned on the front of the leg guard assembly and connected to the elongated pad, an inner ankle pad positioned opposite the elongated pad on the inside of the leg guard assembly, and an elastic positioned at the lowermost portion of the leg guard assembly, the elastic forming a loop that is adapted to secure a foot between the sole and the instep. | 07-25-2013 |
20140331391 | PROTECTIVE HEAD GUARD - A non-rigid head guard assembly, constructed in accordance with this invention, provides superior protection against head collisions. The head guard is circular with a narrower section at the forehead and a wider section at the rear to protect the back of the head. The head guard, at the sections in contact with the temple area of the head and the back of the head, is reinforced with an additional layer of foam, The exterior of the assembly is made of breathable and moisture wicking fabric. The interior protective element consists of either a single layer of viscoelastic polyurethane foam or a dual layer viscoelastic polyurethane foam separated by a thin layer of semi-dry lubricant, which is a low friction material, for enhanced wear and corrosion protection. | 11-13-2014 |
Jing Liang, New York, NY US
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20130333093 | Soccer Goalkeeper Glove - Sports gloves include a multilayer palm section that includes an outer layer and one or more inner layers, at least one of which is a layer of slow rebound, open cell polyurethane to provide a glove with better impact control and protection while also providing a user with better feel for a ball striking the palm. | 12-19-2013 |
20140000016 | Slow Rebound Foam Padded Sports Shirt | 01-02-2014 |
Joanna Jung-Yen Liang, New York, NY US
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20080255922 | PREFERRED COST BIDDING FOR ONLINE ADVERTISING - In an online advertising system, preferred cost bidding allows advertisers to specify a preferred “average” cost target (e.g., cost-per-click (CPC), cost per thousand impressions (CPM)), rather than a “maximum” cost target (e.g., maximum CPC, CPM). The system attempts to bring the advertiser's overall advertising cost as close as possible to the advertiser's specified average cost, using an iterative process (e.g., a feedback loop) that updates bids for keywords using historical performance data for the key words. In some implementations, a bid is automatically adjusted in an adaptive way to compensate for natural changes in fluctuations of the market using historical performance data to compute a bid that is likely to result in an average cost (per click) that is close to the advertiser's preferred average target cost (per click). | 10-16-2008 |
Liang Liang, Yorktown Heights, NY US
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20130266872 | ELECTRODE SEPARATOR - The present invention provides a separator for use in an alkaline electrochemical cell comprising a polymer material and an inert filler comprising zirconium oxide. Examples of polymer materials useful in this invention include ABS polymer material, halogenated alkylene polymer material, and PE polymer material. | 10-10-2013 |
Minghwa Liang, Stony Brook, NY US
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20100285985 | Methods and Systems for the Generation of Plurality of Security Markers and the Detection Therof - This invention pertains to methods for generating large quantities of DNA security markers by combinatorial variation techniques using polymorphic fragment length DNA for unique identification security marker applications such as explosive ink used in dye/smoke pack and cash carrying boxes. | 11-11-2010 |
Ming-Hwa Liang, Stony Brook, NY US
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20080293052 | SYSTEM AND METHOD FOR AUTHENTICATING SPORTS IDENTIFICATION GOODS - A method for authenticating and verifying garment to be genuine is described. The method for authenticating a garment comprises applying a particular nucleic acid material/marker associated with a particular sequence of nucleic acid bases to a dye or paint and applying the marker to the garment. The method also comprises collecting a sample from the garment and verifying the garment is genuine by detecting the particular nucleic acid material on or within the garment. | 11-27-2008 |
20080299559 | METHODS FOR AUTHENTICATING ARTICLES WITH OPTICAL REPORTERS - This invention pertains to methods for authenticating an article comprising tagging the article with light emitting optical reporter particles, and more specifically tagging the articles with up-converting phosphor particles (UCP), linked to nucleic acids of detectable sequence. | 12-04-2008 |
20080299667 | OPTICAL REPORTER COMPOSITIONS - This invention provides compositions that have a light emitting reporter linked to biomolecules, preferably, nucleotide oligomers. The light reporter particles are silylated and functionalized to produce a coated light reporter particle, prior to covalently linking the biomolecules to the light reporter particle. The light reporter particles of the invention can be excited by a light excitation source such as UV or IR light, and when the biomolecule is DNA, the attached DNA molecule(s) are detectable by amplification techniques such as PCR. | 12-04-2008 |
20080312427 | METHODS FOR COVALENT LINKING OF OPTICAL REPORTERS - A method to link a light emitting reporter to biomolecules with nucleotide oligomers is described. The light reporter particles are silylated and functionalized to produce a coated light reporter particle, prior to covalently linking the biomolecules to the light reporter particle. The light reporter particle generated by the methods of the invention can be excited by a light excitation source such as UV or IR light, and when the biomolecule is DNA, the attached DNA molecule(s) are detectable by amplification techniques such as PCR. | 12-18-2008 |
20090042191 | SYSTEM AND METHOD FOR SECURE DOCUMENT PRINTING AND DETECTION - A method for authenticating and verifying an item to be genuine is described. The method for authenticating the item comprises applying a particular nucleic acid material associated with a particular sequence of nucleic acid bases to ink within an ink cartridge or a toner compound within a toner housing. The method also comprises collecting a sample of either the ink or toner compound and verifying the ink or toner is genuine by detecting the particular nucleic acid material. | 02-12-2009 |
20090075261 | SYSTEM AND METHOD FOR AUTHENTICATING TABLETS - A method for authenticating and verifying a pharmaceutical item to be genuine is described. The method for authenticating a tablet comprises applying a particular nucleic acid material associated with a particular sequence of nucleic acid bases to a tablet or capsule. The method also comprises collecting a sample of the tablet and verifying the tablet is genuine by detecting the particular nucleic acid material. | 03-19-2009 |
20100279282 | METHODS FOR GENOTYPING MATURE COTTON FIBERS AND TEXTILES - Methods for distinguishing between cotton cultivars of a specific species by analyzing a sample of mature cotton fibers from raw cotton materials or from textile goods are disclosed. DNA is extracted from the mature cotton fiber sample and subjected to PCR techniques which enable the identification of the cultivar of a particular cotton species utilized in the textile or cotton material of interest. | 11-04-2010 |
20110250594 | METHODS FOR GENETIC ANALYSIS OF TEXTILES MADE OF GOSSYPIUM BARBADENSE AND GOSSYPIUM HIRSUTUM COTTON - Methods for distinguishing between cotton species by analyzing a sample of mature cotton fibers from raw cotton materials or from textile goods are disclosed. DNA is extracted from the mature cotton fiber sample and subjected to PCR techniques which enable the identification of the species of cotton utilized in the textile or cotton material of interest. | 10-13-2011 |
20120252025 | METHODS FOR COVALENT LINKING OF OPTICAL REPORTERS - A method to link a light emitting reporter to biomolecules with nucleotide oligomers is described. The light reporter particles are silylated and functionalized to produce a coated light reporter particle, prior to covalently linking the biomolecules to the light reporter particle. The light reporter particle generated by the methods of the invention can be excited by a light excitation source such as UV or IR light, and when the biomolecule is DNA, the attached DNA molecule(s) are detectable by amplification techniques such as PCR. | 10-04-2012 |
Minghwa Benjamin Liang, Stony Brook, NY US
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20090286250 | INCORPORATING SOLUBLE SECURITY MARKERS INTO CYANOACRYLATE SOLUTIONS - Methods for authenticating an article with a cyanoacrylate solution comprising a water soluble security marker compound are described. The methods for producing a nucleophilic security marker/cyanoacrylate solution as well as methods for labeling an item and detecting the nucleophilic security marker/cyanoacrylate from an item being authenticated are also described. A method for using a nucleophilic cyanoacrylate security marker for antitheft purposes is also described. | 11-19-2009 |
20150329856 | METHODS AND SYSTEMS FOR THE GENERATION OF A PLURALITY OF SECURITY MARKERS AND THE DETECTION THEROF - This invention pertains to methods for generating large quantities of DNA security markers by combinatorial variation techniques using polymorphic fragment length DNA for unique identification security marker applications such as explosive ink used in dye/smoke pack and cash carrying boxes. | 11-19-2015 |
Minghwa Benjamin Liang, East Setauket, NY US
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20140099643 | USE OF PERTURBANTS TO FACILITATE INCORPORATION AND RECOVERY OF TAGGANTS FROM POLYMERIZED COATINGS - The invention provides methods for increasing the recoverability of taggants from an object. The methods include the steps of incorporating a taggant into a solution; mixing the solution including the taggant with a perturbant to form a first perturbant taggant solution; mixing the first perturbant taggant solution with a polymer to form a second perturbant taggant polymer solution; and applying the second perturbant taggant polymer solution to at least a portion of the object to form a taggant-coated object. Methods for authentication of a taggant marked object are also provided. | 04-10-2014 |
20140102899 | PLASMA TREATMENT FOR DNA BINDING - The invention provides a composition including DNA bonded to a plasma-treated surface, the plasma can be any suitable plasma, such as an argon plasma, a compressed air plasma, a flame-based plasma or a vacuum plasma. Surfaces treatable by the methods of the invention include ceramic, metal, fabric and organic polymer surfaces. The DNA can be any DNA, such as a marker DNA, which can be linear or circular, single-stranded or double stranded and from about 25 bases to about 10,000 bases in length. Also provided is a method of binding DNA to a surface, including the steps of exposing the surface to a plasma to produce a plasma-treated surface; and applying DNA to the plasma-treated surface to produce surface bound DNA on the treated surface. A system for binding DNA to a surface is also disclosed, the system includes a plasma generator adapted to treating a surface with a plasma to produce a plasma-treated surface; and an applicator containing DNA adapted to applying DNA to the plasma-treated surface to produce surface bound DNA on the plasma-treated surface. | 04-17-2014 |
20140106357 | SECURITY SYSTEM AND METHOD OF MARKING AN INVENTORY ITEM AND/OR PERSON IN THE VICINITY - A method of marking an inventory item includes providing an activatable smoke generator and a reservoir for holding a smoke fluid and adapted to provide a flow of smoke fluid to the generator. The reservoir contains a smoke fluid including a carrier nucleic acid having a uniquely identifiable sequence, and upon activation of the smoke generator, marker smoke is generated and targeted to flow over the inventory item. The method further includes activating the smoke generator to produce the marker smoke including the carrier nucleic acid so as to cause the marker smoke to flow over the inventory item and thereby to detectably mark the inventory item with carrier nucleic acid. | 04-17-2014 |
20140256881 | ALKALINE ACTIVATION FOR IMMOBILIZATION OF DNA TAGGANTS - The invention provides methods for stably binding and immobilizing deoxyribonucleic acid onto objects and substrates. The method includes exposing the deoxyribonucleic acid to alkaline conditions, and contacting the deoxyribonucleic acid to the object or substrate. The alkaline conditions are produced by mixing the deoxyribonucleic acid with an alkaline solution having a pH of about 9.0 or higher, and contacting the deoxyribonucleic acid to the substrate. The immobilized DNA can be used as a taggant and can be used in combination with other detectable taggants, such as optical reporters. Methods for authentication of a DNA marked object are also provided. | 09-11-2014 |
20140272097 | DNA MARKING OF PREVIOUSLY UNDISTINGUISHED ITEMS FOR TRACEABILITY - The invention provides a method of marking an item with a naturally-derived or synthetic non-natural polymeric marker molecules, such as a DNA or Peptide marker in conjunction with optional visible or rapid scan reporters for authenticating or tracking, in which the method includes providing an item for marking, and applying a medium including a DNA marker to the item. The invention also provides a method of marking an item with a DNA marker for authenticating or tracking, in which the method includes providing a medium including a DNA marker, and molding the medium including the DNA marker to provide all or part of the item. The DNA marker encodes information unique to the item and/or the model of the item as desired. | 09-18-2014 |
20140295423 | METHODS FOR GENETIC ANALYSIS OF TEXTILES MADE OF GOSSYPIUM BARBADENSE AND GOSSYPIUM HIRSUTUM COTTON - Methods for distinguishing between cotton species by analyzing a sample of mature cotton fibers from raw cotton materials or from textile goods are disclosed. DNA is extracted from the mature cotton fiber sample and subjected to PCR techniques which enable the identification of the species of cotton utilized in the textile or cotton material of interest. | 10-02-2014 |
20150018538 | METHOD AND DEVICE FOR MARKING ARTICLES - Provided are a method and device for marking an article for security, tracking or authentication. The method includes depositing a solution comprising a nucleic acid marker onto at least a portion of the article. The nucleic acid marker may be activated, for example, by adding a functional group to the nucleic acid marker. The activation of the nucleic acid marker may be performed by exposure to alkaline conditions. The method is well suited for marking fibers and textiles, as well as many other items. | 01-15-2015 |
20150083797 | VERIFICATION OF PHYSICAL ENCRYPTION TAGGANTS USING DIGITAL REPRESENTATIVES AND AUTHENTICATIONS THEREOF - A verifiably identifiable object that includes a primary taggant encoding a readable encrypted first identifier of the object encrypted by a first method and a secondary taggant encoding a readable encrypted second identifier of the object optionally encrypted by a second method. The primary taggant can be a physical identification taggant, such as DNA including an authentication sequence, and the secondary taggant can be a digital identification taggant. The digital identification taggant encodes information validating the physical identification taggant, such as by referencing information embodied in the physical taggant, e.g. the defined sequence within the DNA. Also included is a method and system for identification and/or authentication of an object that includes a primary taggant encoding a readable encrypted first identifier of the object encrypted by a first method and a secondary taggant encoding a readable encrypted second identifier of the object encrypted by a second method. | 03-26-2015 |
20150107475 | DNA MARKING OF PREVIOUSLY UNDISTINGUISHED ITEMS FOR TRACEABILITY - The invention provides a method of marking an item with naturally-derived or synthetic non-natural polymeric marker molecules, such as a DNA or Peptide marker in conjunction with optional visible or rapid scan reporters for authenticating or tracking, in which the method includes providing an item for marking, and applying a medium including a DNA marker to the item. The invention further provides methods for stably binding and immobilizing activated deoxyribonucleic acid onto objects and substrates. The method includes exposing the deoxyribonucleic acid to alkaline conditions, and contacting the deoxyribonucleic acid to the object or substrate. Also provided are methods for increasing the recoverability of taggants from an object. The methods include the steps of incorporating a taggant into a solution; mixing the solution including the taggant with a perturbant to form a first perturbant taggant solution; mixing the first perturbant taggant solution with a polymer to form a second perturbant taggant polymer solution; and applying the second perturbant taggant polymer solution to at least a portion of the object to form a taggant-coated object. The invention also provides a method of marking an item with a DNA marker for authenticating or tracking, in which the method includes providing a medium including a DNA marker, and molding the medium including the DNA marker to provide all or part of the item. The DNA marker encodes information unique to the item and/or the model of the item as desired. | 04-23-2015 |
20150141264 | IN-FIELD DNA EXTRACTION, DETECTION AND AUTHENTICATION METHODS AND SYSTEMS THEREFOR - The invention provides a method for in-field detection of a distinctive marker. The method includes providing a sample from an article of interest and analyzing the sample to detect the presence of the distinctive marker. The analysis is performed using an in-field detection instrument. The in-field detection instrument includes a microsystem configured to perform sample in-answer out analysis and detect the presence of the distinctive marker in the sample. | 05-21-2015 |
20150191799 | METHODS FOR GENOTYPING MATURE COTTON FIBERS AND TEXTILES - Methods for distinguishing between cotton cultivars of a specific species by analyzing a sample of mature cotton fibers from raw cotton materials or from textile goods are disclosed. DNA is extracted from the mature cotton fiber sample and subjected to PCR techniques which enable the identification of the cultivar of a particular cotton species utilized in the textile or cotton material of interest. | 07-09-2015 |
20150232952 | QUANTITATIVE GENETIC ANALYSIS OF ARTICLES INCLUDING GOSSYPIUM BARBADENSE AND GOSSYPIUM HIRSUTUM COTTON - Exemplary embodiments of the present invention provide a method for assessing a proportion of one or more cotton species in an article comprising cotton. The method includes providing a sample including cotton fibers from the article comprising cotton. Cotton DNA is extracted from the cotton fibers to provide extracted cotton DNA. The extracted cotton DNA is analyzed to identify a presence of one or more cotton species included in the article comprising cotton. Proportions of the one or more cotton species included in the article comprising cotton are assessed. | 08-20-2015 |
20150266332 | ENCRYPTED OPTICAL MARKERS FOR SECURITY APPLICATIONS - Encrypted markers that are not readily detectable can be revealed by treatment with a specific reagent used as a developer to reveal a readily detectable physical property of the marker, such as a characteristic fluorescence emission after excitation with a particular excitation wavelength, or to reveal a visible color. The encrypted marker can be developed in situ, or a sample can be removed by brushing, scraping, swabbing or scratching the marked object or item and developing the encrypted marker or a sample thereof with the appropriate developer to reveal an overt marker or optical signal. The marker can be revealed by exposure of the encrypted marker or a sample thereof to the developer in any suitable form, such as a solution, a slurry, a swab, a solid (such as in granular form), or a gas or a vapor that includes a developer. | 09-24-2015 |
20150275271 | PLASMA TREATMENT FOR DNA BINDING - The invention provides a composition including DNA bonded to a plasma-treated surface, the plasma can be any suitable plasma, such as an argon plasma, a compressed air plasma, a flame-based plasma or a vacuum plasma. Surfaces treatable by the methods of the invention include ceramic, metal, fabric and organic polymer surfaces. The DNA can be any DNA, such as a marker DNA, which can be linear or circular, single-stranded or double stranded and from about 25 bases to about 10,000 bases in length. Also provided is a method of binding DNA to a surface, including the steps of exposing the surface to a plasma to produce a plasma-treated surface; and applying DNA to the plasma-treated surface to produce surface bound DNA on the treated surface. A system for binding DNA to a surface is also disclosed, the system includes a plasma generator adapted to treating a surface with a plasma to produce a plasma-treated surface; and an applicator containing DNA adapted to applying DNA to the plasma-treated surface to produce surface bound DNA on the plasma-treated surface. | 10-01-2015 |
20150302713 | SECURITY SYSTEM AND METHOD OF MARKING AN INVENTORY ITEM AND/OR PERSON IN THE VICINITY - A method of marking an inventory item includes providing an activatable smoke generator and a reservoir for holding a smoke fluid and adapted to provide a flow of smoke fluid to the generator. The reservoir contains a smoke fluid including a carrier nucleic acid having a uniquely identifiable sequence, and upon activation of the smoke generator, marker smoke is generated and targeted to flow over the inventory item. The method further includes activating the smoke generator to produce the marker smoke including the carrier nucleic acid so as to cause the marker smoke to flow over the inventory item and thereby to detectably mark the inventory item with carrier nucleic acid. | 10-22-2015 |
20150304109 | CONTOUR ENCRYPTION AND DECRYPTION - A method of encrypting information includes converting an information sequence represented as a strings of bits into a curvilinear coding system, where each element of the curvilinear coding system corresponds to a sub-sequence of successive same-valued bits, converting said curvilinear coding system into a at least one closed curve, and embedding said at least one closed curve in a 2-dimensional pattern. A method for decrypting information includes extracting at least one closed curve from a digitized 2-dimensional pattern, and converting the at least one closed curve into an information sequence represented as a string of bits. | 10-22-2015 |
20160102215 | INCORPORATING SOLUBLE SECURITY MARKERS INTO CYANOACRYLATE SOLUTIONS - Methods for authenticating an article with a cyanoacrylate solution comprising a water soluble security marker compound are described. The methods for producing a nucleophilic security marker/cyanoacrylate solution as well as methods for labeling an item and detecting the nucleophilic security marker/cyanoacrylate from an item being authenticated are also described. A method for using a nucleophilic cyanoacrylate security marker for antitheft purposes is also described. | 04-14-2016 |
Qingqing Liang, Lagrangeville, NY US
Patent application number | Description | Published |
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20100264469 | MOSFET INCLUDING EPITAXIAL HALO REGION - A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically specifically within a channel region pedestal within the metal oxide semiconductor field effect transistor structure. The halo region aperture is filled with a halo region formed using an epitaxial method, thus the halo region may be formed physically separated from the gate dielectric. As a result, performance of the metal oxide semiconductor field effect transistor is enhanced. | 10-21-2010 |
20110169082 | METHOD FOR FORMING RETROGRADED WELL FOR MOSFET - A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed. | 07-14-2011 |
20110169088 | STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) - A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided. | 07-14-2011 |
20120091514 | Semiconductor Junction Diode Device And Method For Manufacturing The Same - A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level. | 04-19-2012 |
20120139044 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced. | 06-07-2012 |
20120146103 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than | 06-14-2012 |
20120153389 | STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) - A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided. | 06-21-2012 |
20120168863 | Semiconductor Structure and Method for Manufacturing the Same - Semiconductor structure and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device is formed on an SOI substrate comprising an SOI layer, a buried insulating layer, a buried semiconductor layer and a semiconductor substrate from top to bottom, and comprises: source/drain regions formed in the SOI layer; a gate formed on the SOI layer, wherein the source/drain regions are located at both sides of the gate; a back gate region formed by a portion of the buried semiconductor layer which is subjected to resistance reduction; and a first isolation structure and a second isolation structure which are located at both sides of the source/drain regions and extend into the SOI substrate; wherein the first isolation structure and the second isolation structure laterally adjoin the SOI layer at a first side surface and a second side surface respectively; the first isolation structure laterally adjoins the buried semiconductor layer at a third side surface; and the third side surface is located between the first side surface and the second side surface. | 07-05-2012 |
20120191392 | METHOD FOR ANALYZING CORRELATIONS AMONG DEVICE ELECTRICAL CHARACTERISTICS AND METHOD FOR OPTIMIZING DEVICE STRUCTURE - A method for analyzing correlations among electrical characteristics of an electronic device and a method for optimizing a structure of the electronic device are disclosed. The electronic device may comprises a plurality of electrical characteristics v | 07-26-2012 |
20120261727 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING LOCAL INTERCONNECT STRUCTURE THEREOF - A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth. | 10-18-2012 |
20120261759 | Semiconductor device and method for manufacturing the same - A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance. | 10-18-2012 |
20120261790 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices. | 10-18-2012 |
20120267725 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects. | 10-25-2012 |
20120273886 | EMBEDDED SOURCE/DRAIN MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate. | 11-01-2012 |
20120281468 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage V | 11-08-2012 |
20120286337 | FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance. | 11-15-2012 |
20120286373 | GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value. | 11-15-2012 |
20120290998 | DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD - The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation. | 11-15-2012 |
20120309139 | METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR - An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device. | 12-06-2012 |
20120326155 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET. | 12-27-2012 |
20120326231 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate. | 12-27-2012 |
20130001665 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate. | 01-03-2013 |
20130001690 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via. | 01-03-2013 |
20130009244 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction. | 01-10-2013 |
20130015526 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEAANM Liang; QingqingAACI LagrangevilleAAST NYAACO USAAGP Liang; Qingqing Lagrangeville NY USAANM Zhu; HuilongAACI PoughkeepsieAAST NYAACO USAAGP Zhu; Huilong Poughkeepsie NY USAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA US - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device. | 01-17-2013 |
20130020578 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region. | 01-24-2013 |
20130020618 | SEMICONDUCTOR DEVICE, FORMATION METHOD THEREOF, AND PACKAGE STRUCTURE - A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating. | 01-24-2013 |
20130037859 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application. | 02-14-2013 |
20130045588 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved. | 02-21-2013 |
20130049125 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices. | 02-28-2013 |
20130062708 | SEMICONDUCTOR DEVICE STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING FIN - A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices. | 03-14-2013 |
20130069041 | METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME - A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer. | 03-21-2013 |
20130069112 | SRAM CELL AND METHOD FOR MANUFACTURING THE SAME - A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may comprise a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may comprise a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may comprise a plurality of semiconductor sub-layers. The first and second fins can comprise different number of the semiconductor sub-layers and have different heights from each other. | 03-21-2013 |
20130069167 | SRAM CELL AND METHOD FOR MANUFACTURING THE SAME - A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise: a semiconductor layer; and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the semiconductor layer, wherein the first FinFET comprises a first fin formed by patterning the semiconductor layer, the first fin having a first top surface and a first bottom surface, wherein the second FinFET comprises a second fin formed by patterning the semiconductor layer, the second fin having a second top surface and a second bottom surface, and wherein the first top surface is substantially flush with the second top surface, the first and second bottom surfaces abut against the semiconductor layer, and the height of the second fin is greater than the height of the first fin. | 03-21-2013 |
20130093002 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate. | 04-18-2013 |
20130093020 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks. | 04-18-2013 |
20130093041 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device. | 04-18-2013 |
20130099315 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region. | 04-25-2013 |
20130140624 | Semiconductor Structure and Method for Forming The Semiconductor Structure - The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer. | 06-06-2013 |
20130153913 | Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor - A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. | 06-20-2013 |
20130221329 | Graphene Device - An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc. | 08-29-2013 |
20130299885 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin. | 11-14-2013 |
20130341713 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer. | 12-26-2013 |
20140110756 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer. | 04-24-2014 |
20140124847 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer. | 05-08-2014 |
20140131806 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same is disclosed. In one aspect, the method comprises forming a first MOSFET having a first gate length in a semiconductor substrate, and forming a second MOSFET having a second gate length in the semiconductor substrate. Furthermore, the second gate length is less than the first gate length, and wherein the second MOSFET has a gate stack in the form of a spacer having a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor substrate. | 05-15-2014 |
20140256109 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region to increase carrier mobility and improve performances of the device. | 09-11-2014 |
20150054073 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate. | 02-26-2015 |
20150054074 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer. | 02-26-2015 |
20150076602 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure, comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance. | 03-19-2015 |
20150187942 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device. | 07-02-2015 |
20150200275 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin. | 07-16-2015 |
20150221768 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a semiconductor structure is disclosed. The method comprises: providing a substrate, forming a gate stack on the substrate and forming source/drain regions within the substrate; etching the source/drain regions to form trenches; forming a contact layer on the surface of the source/drain regions that have been etched; forming a stress material layer within the trenches; depositing an interlayer dielectric layer and forming contact plugs in contact with the stress material. Accordingly, a semiconductor structure is also disclosed. In the present invention, trenches are formed by etching source/drain regions in order to increase exposed areas at the source/drain regions, a contact layer is formed on the surface of the source/drain regions, and a stress material is filled into the trenches, which is capable of reducing effectively contact resistance between the contact layer and source/drain regions while introducing stress into channels, and thereby enhancing carrier mobility and improving performance of semiconductor structures. | 08-06-2015 |
20150228735 | Semiconductor Device And Method For Manufacturing The Same - The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device. The present invention is capable of eliminating pathway for leakage current between source/drain regions and SOI substrate at the meantime of reducing contact resistance at source/drain regions. | 08-13-2015 |
20150236134 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process. | 08-20-2015 |
20150243598 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners. | 08-27-2015 |
20150243654 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending along one direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings that span over the gate lines: c) implanting ions into the gate lines, such that the gate lines are insulated at the openings. The present invention enables the gate lines to maintain complete shape at formation of electrically isolated gates, which will not cause defects that exist in the prior art when forming a dielectric layers at subsequent steps, thereby guaranteeing performance of semiconductor devices. Additionally, the present invention further provides a semiconductor structure manufactured according to the method provided by the present invention. | 08-27-2015 |
20150255594 | QUASI-NANOWIRE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer ( | 09-10-2015 |
20150255609 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions. | 09-10-2015 |
20150270399 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer ( | 09-24-2015 |
20150279745 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES - There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction. | 10-01-2015 |
20150279992 | METHOD OF MANUFACTURING FIN FIELD EFFECT TRANSISTOR - The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer ( | 10-01-2015 |
20150287828 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack. | 10-08-2015 |
20150295067 | METHOD FOR MANUFACTURING P-TYPE MOSFET - The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer. | 10-15-2015 |
20150311319 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings. | 10-29-2015 |
20150318390 | FINFET AND METHOD OF MANUFACTURING THE SAME - A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first region, the first region being one of a source region and a drain region. The method further includes forming a sacrificial spacer. The method further includes forming a second region with the sacrificial spacer as a mask, the second region being the other one of the source region and the drain region. The method further includes removing the sacrificial spacer. The method further includes replacing the sacrificial spacer with a gate stack comprising a gate conductor and a gate dielectric that separates the gate conductor from the semiconductor fin. | 11-05-2015 |
20150332973 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention. | 11-19-2015 |
Qingqing Liang, Langrangeville, NY US
Patent application number | Description | Published |
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20130015529 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA USAANM Liang; QingqingAACI LangrangevilleAAST NYAACO USAAGP Liang; Qingqing Langrangeville NY USAANM Ying; HaizhouAACI PoughkeepsieAAST NYAACO USAAGP Ying; Haizhou Poughkeepsie NY US - There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits. | 01-17-2013 |
Qingqing Liang, Hopewell Junction, NY US
Patent application number | Description | Published |
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20110006371 | INDUCING STRESS IN CMOS DEVICE - A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening. | 01-13-2011 |
20110031554 | STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC - A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process. | 02-10-2011 |
20110059587 | DEVICE HAVING SELF-ALIGNED DOUBLE GATE FORMED BY BACKSIDE ENGINEERING, AND DEVICE HAVING SUPER-STEEP RETROGRADED ISLAND - A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided. | 03-10-2011 |
20120007190 | STRESS-INDUCED CMOS DEVICE - A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET. | 01-12-2012 |
Qingqing Liang, Poughkeepsie, NY US
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20140027864 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer. | 01-30-2014 |
Qingqing Liang, New York, NY US
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20120187496 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced. | 07-26-2012 |
20120187497 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits. | 07-26-2012 |
Richard Liang, Brooklyn, NY US
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20150371316 | System and a Method for Automatically Detecting and Processing Physical Events Indicative of Status of an Order and Notifying Customers of the Same - The present invention provides a system and a method for automatically detecting and processing physical events indicative of status of an order and notifying customers of the same. The method includes receiving an order from a client device. The order includes at least one item selected for purchase. The method also includes retrieving data including time for preparation of the item selected for the purchase and alerting of an existence of the order. The method also includes automatically detecting a physical event associated with the order. The physical event identifies commencement of the order. The method also includes automatically converting the physical event to a status of the order including an estimated time for completion of the order. The estimated time is calculated in view of the retrieved data and the physical event associated with the order. The method further includes transmitting the status of the order to the client device. | 12-24-2015 |
Scott Frank Liang, New York, NY US
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20160080438 | Method and Apparatus for Tile-Based Geographic Social Interaction - Tile-based geographic discussion platform may be provided through a location-aware map overlaid with a grid comprising a plurality of tiles. Each tile may be linked to a unique portion of the map and provide location-specific information to the user. A user may provide input with respect to a tile. | 03-17-2016 |
Sherry Liang, Staten Island, NY US
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20120059548 | POWERED MOBILITY SYSTEMS AND METHODS - Powered mobility systems and methods are disclosed. A powered mobility system includes a mobile unit, a support frame, a plurality of markers, a motion capture device, and a processor. The mobile unit is operable to move the powered mobility system. The support frame is adapted to support a user. The plurality of markers are configured to be attached to the user. The motion capture device is configured to detect movement of the plurality of markers. The processor is programmed to receive signals from the motion capture device, translate the signals into instructions for moving the mobile unit, and transmit the instructions to the mobile unit. A powered mobility method includes placing a user in a support frame, attaching a plurality of markers to the user, detecting movement of the plurality of the markers, and generating movement of the mobile unit based on the movement of the plurality of the markers. | 03-08-2012 |
Shurong Liang, Poughkeepsie, NY US
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20150093887 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITSI - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeO | 04-02-2015 |
20150303249 | METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES - Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases. | 10-22-2015 |
20150318176 | FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY BY PERFORMING AN IMPLANTATION/ANNEAL DEFECT GENERATION PROCESS - One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material. | 11-05-2015 |
Wayne Liang, Nesconset, NY US
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20090131036 | Providing a High-Speed Connection Between a Memory Medium of a Mobile Device and an External Device - System and method for providing a high speed connection to a memory medium of a mobile device. The mobile device may be a mobile phone or other type of portable electronic device. The memory medium may be removable and/or may be flash memory, as desired. The mobile device may include a USB hub that provides a direct high speed connection between an external device and a memory medium of the mobile device. The USB hub may also provide a connection (possibly high speed) between the external device and the processor of the mobile device. The mobile device may also include a high speed connection between the processor of the mobile device and the memory medium. | 05-21-2009 |
20100049895 | Providing a Connection Between a Memory Medium of a Mobile Device and an External Device - System and method for providing a high speed connection to a memory medium of a mobile device. The mobile device may be a mobile phone or other type of portable electronic device. The memory medium may be removable and/or may be flash memory, as desired. The mobile device may include a USB hub that provides a direct high speed connection between an external device and a memory medium of the mobile device. The USB hub may also provide a connection (possibly high speed) between the external device and the processor of the mobile device. The mobile device may also include a high speed connection between the processor of the mobile device and the memory medium. | 02-25-2010 |
Xiaoping Liang, Hopewell Junction, NY US
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20160079394 | NANOWIRE STRUCTURE WITH SELECTED STACK REMOVED FOR REDUCED GATE RESISTANCE AND METHOD OF FABRICATING SAME - Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers. | 03-17-2016 |
Xiaotao Liang, Dix Hills, NY US
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20100103064 | PARASITIC DIPOLE ASSISTED WLAN ANTENNA - A parasitic dipole assisted WLAN antenna for creating a second resonance in the A band and providing greater bandwidth usage to a mobile computing or communication device. A secondary B/G band monopole antenna is connected to the A band antenna at the point of maximum impedance of the A band providing minimal interference between the two bands. The dipole structure antennas are connected at the A band loop antenna feed pin and ground pin. | 04-29-2010 |
20110140977 | COMPACT DUAL-MODE UHF RFID READER ANTENNA SYSTEMS AND METHODS - The present disclosure relates to compact, dual-mode ultra high frequency (UHF) radio frequency identification (RFID) reader antenna systems and methods capable of supporting both long range and short range applications. The present invention includes a dual-mode antenna design, a dual-mode RFID reader utilizing the dual-mode antenna design, and an associated usage method. The dual-mode antenna design may include a patch operating mode for long range applications and a slot operating mode for short range applications. Additionally, the dual-mode antenna design may include mechanisms to improve the patch operating mode bandwidth, circular polarization in the patch operating mode, and dual polarization in the slot operation mode. | 06-16-2011 |
Xiaotao Liang, East Northport, NY US
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20120306707 | Low-Profile Multiband Antenna For a Wireless Communication Device - A device for wireless communication including a wireless transceiver, a printed circuit board (PCB) coupled to the wireless transceiver, a first antenna and a second antenna. The first antenna is coupled to the PCB at a feed point and grounded at a ground point. The first antenna is a quarter-wavelength antenna communicating signals with the wireless transceiver at a first frequency band. The second antenna is coupled to the first antenna at the feed point and grounded at a further ground point. The second antenna is a half-wavelength antenna communicating signals with the wireless transceiver at a second frequency band. | 12-06-2012 |
20130082933 | MOBILE COMPUTER WITH KEYPAD-EMBEDDED RFID ANTENNA - A mobile computer is described. The mobile computer includes a memory for storing a software application. A processor is coupled to the memory for executing the software application. A display is coupled to the processor for graphically displaying information generated by the software application. A keypad is coupled to the processor for receiving input from a user. The keypad is positioned adjacent to the display. A radio-frequency identification (RFID) antenna is embedded in a portion of the keypad. The RFID antenna includes at least one conductor forming at least one loop for communicating with a RFID device to receive information from the RFID device. | 04-04-2013 |
20130248601 | MOBILE COMPUTER WITH INTEGRATED NEAR FIELD COMMUNICATION ANTENNA - A mobile computer is described. The mobile computer includes a memory for storing a software application. A processor is coupled to the memory for executing the software application. A display is coupled to the processor for graphically displaying information generated by the software application. A card reader having a slot is coupled to the processor for receiving input from a data card. A radio frequency identification (RFID) antenna is embedded in a portion of the card reader proximate to the slot. The RFID antenna includes at least one conductor that forms at least one loop for communicating with an RFID device positioned at least partially within the slot. | 09-26-2013 |
Yong Liang, Niskayuna, NY US
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20140246083 | PHOTOVOLTAIC DEVICES AND METHOD OF MAKING - A photovoltaic device is presented. The photovoltaic device includes a buffer layer disposed on a transparent conductive oxide layer; a window layer disposed on the buffer layer; and an interlayer interposed between the transparent conductive oxide layer and the window layer. The interlayer includes a metal species, wherein the metal species includes gadolinium, beryllium, calcium, barium, strontium, scandium, yttrium, hafnium, cerium, lutetium, lanthanum, or combinations thereof. A method of making a photovoltaic device is also presented | 09-04-2014 |
20140326315 | PHOTOVOLTAIC DEVICES AND METHOD OF MAKING - A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer comprises selenium, wherein an atomic concentration of selenium varies across a thickness of the absorber layer. The photovoltaic device is substantially free of a cadmium sulfide layer. | 11-06-2014 |
20140360565 | PHOTOVOLTAIC DEVICES AND METHOD OF MAKING - A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer includes selenium, and an atomic concentration of selenium varies non-linearly across a thickness of the absorber layer. A method of making a photovoltaic device is also presented. | 12-11-2014 |
20160005885 | Method of Making Photovoltaic Devices - A photovoltaic device is presented. The photovoltaic device includes a buffer layer disposed on a transparent conductive oxide layer; a window layer disposed on the buffer layer; and an interlayer interposed between the transparent conductive oxide layer and the window layer. The interlayer includes: (i) a compound including magnesium and a metal species, wherein the metal species includes tin, indium, titanium, or combinations thereof; or (ii) a metal alloy including magnesium; or (iii) a compound comprising magnesium and fluorine; or (iv) combinations thereof. Method of making a photovoltaic device is also presented. | 01-07-2016 |
20160005916 | Method of Making Photovoltaic Devices - A method of making a photovoltaic device is presented. The method includes disposing a capping layer on a transparent conductive oxide layer, wherein the capping layer includes elemental magnesium, a magnesium alloy, a binary magnesium oxide, or combinations thereof. The method further includes disposing a window layer on the capping layer; and forming an interlayer between the transparent conductive oxide layer and the window layer, wherein the interlayer includes magnesium. | 01-07-2016 |
Yuaxin Liang, South Setauket, NY US
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20100298200 | Compounds and assays for controlling Wnt activity - The present invention relates to the field of therapeutic methods to screen for compounds on the basis of their ability to influence Wnt activity. The screening process is applied to both a physical library of a series of compounds and a virtual library of compounds that affect Wnt activity. In one aspect, the virtual screening process could be carried out where a permutational library of small peptides is substituted for the small organic molecules. The inventive methods may be used to empirically test for effects on Wnt activity and may also be applied to any pair of proteins involved in protein-protein interactions. | 11-25-2010 |
20120322717 | Compounds and assays for controlling Wnt activity - The present invention relates to the field of therapeutic methods to screen for compounds on the basis of their ability to influence Wnt activity. The screening process is applied to both a physical library of a series of compounds and a virtual library of compounds that affect Wnt activity. In one aspect, the virtual screening process could be carried out where a permutational library of small peptides is substituted for the small organic molecules. The inventive methods may be used to empirically test for effects on Wnt activity and may also be applied to any pair of proteins involved in protein-protein interactions. | 12-20-2012 |
Yue Liang, Hopewell Junction, NY US
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20100289085 | Asymmetric Semiconductor Devices and Method of Fabricating - A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material. | 11-18-2010 |
20110163385 | ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure. | 07-07-2011 |
20120171831 | ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME - A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer. | 07-05-2012 |
Yue Liang, Fishkill, NY US
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20130105894 | THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS | 05-02-2013 |
20130105896 | Threshold Voltage Adjustment For Thin Body Mosfets | 05-02-2013 |
20140191295 | DUMMY GATE INTERCONNECT FOR SEMICONDUCTOR DEVICE - A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer. | 07-10-2014 |
Yue Liang, Beacon, NY US
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20100187610 | SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE - A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO | 07-29-2010 |
20100237435 | METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY - A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature. | 09-23-2010 |
20100258881 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 10-14-2010 |
20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 11-04-2010 |
20110180880 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 07-28-2011 |
20120043622 | PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE - Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state. | 02-23-2012 |
20120091506 | Method and Structure for pFET Junction Profile With SiGe Channel - A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed. | 04-19-2012 |
20120108017 | THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 05-03-2012 |
20120126335 | METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY - A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature. | 05-24-2012 |
20130087832 | Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided. | 04-11-2013 |
20130087859 | Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 04-11-2013 |
20130099281 | POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION - Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches. | 04-25-2013 |
20130126976 | SELECTIVE PARTIAL GATE STACK FOR IMPROVED DEVICE ISOLATION - A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure. | 05-23-2013 |
20130168695 | CMOS HAVING A SIC/SIGE ALLOY STACK - A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer. | 07-04-2013 |
20130168776 | Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 07-04-2013 |
20140349451 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 11-27-2014 |
Zhengrong Liang, Stony Brook, NY US
Patent application number | Description | Published |
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20110237929 | BLADDER WALL THICKNESS MAPPING FOR TUMOR DETECTION - Disclosed is a method and apparatus for detection of a bladder wall tumor. Layers of a bladder wall are created by magnetic resonance imaging. A group of voxels having a lowest intensity is identified in a layer and an energy function modification enlarges the layer of the bladder wall. A partial volume image segmentation obtains tissue type mixture percentages in each voxel near inner and outer borders of the bladder wall in the layer of the bladder wall to obtain a bladder wall thickness. A range of uncertainty at the inner and outer borders of the bladder wall is obtained, and integration is performed of the bladder wall thickness along a path starting at a point on the outer border and ending at a corresponding point on the inner border. | 09-29-2011 |
20150030227 | COMPUTERIZED IMAGE RECONSTRUCTION METHOD AND APPARATUS - Provided herein is a computerized image reconstruction apparatus and method that includes recording projection path information and energy loss information of a plurality of particles traversing an object being imaged and determining an estimated image of the object based on the projection path information and the energy loss information sampled into a projection format. The estimated image includes an active volume defined by an enclosure border. Cost function minimization uses an Adaptive-weighted Total Variation cost function, a Penalized Weighted Least-Squares cost function, or an Alpha-Divergence cost function to update the estimated image. An iterative updating algorithm corresponding to the cost function updates the estimated image and produces a final image based on the estimated image according to a predetermined threshold. | 01-29-2015 |
20150073259 | SYSTEM AND METHOD FOR CT-GUIDED NEEDLE BIOPSY - An image-guided system and method for performing needle biopsy on a moving lung nodule of a body is provided. CT images of the lung nodule are obtained to generate a motion model, based on which an optimal needle advancing path is determined. The motion of the lung nodule and the motion of a fiducial marker attached to the body are correlated. The motion of the fiducial marker is tracked and monitored by a camera to determine a position of the lung nodule based on the correlation. A time for advancing the needle is determined based on a motion attribute of the reference. The needle is advanced by a robotic needle manipulator at the predetermined time along the path to accomplish the needle placement. | 03-12-2015 |