Patent application number | Description | Published |
20100187610 | SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE - A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO | 07-29-2010 |
20110215405 | PREVENTION OF OXYGEN ABSORPTION INTO HIGH-K GATE DIELECTRIC OF SILICON-ON-INSULATOR BASED FINFET DEVICES - A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing. | 09-08-2011 |
20110221012 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 09-15-2011 |
20110248350 | METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG) - Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated. | 10-13-2011 |
20110269276 | METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES - In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer. | 11-03-2011 |
20110291198 | Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices - A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device. | 12-01-2011 |
20120068261 | Replacement Metal Gate Structures for Effective Work Function Control - A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. | 03-22-2012 |
20120119204 | Replacement Gate Having Work Function at Valence Band Edge - Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly. | 05-17-2012 |
20120132998 | Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current - The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures. | 05-31-2012 |
20120139053 | Replacement Gate Devices With Barrier Metal For Simultaneous Processing - A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate. | 06-07-2012 |
20120181616 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 07-19-2012 |
20120181630 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. | 07-19-2012 |
20120187420 | STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL - An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure. | 07-26-2012 |
20120196424 | METHOD OF FABRICATING A DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR - A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material. | 08-02-2012 |
20120214299 | METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG) - Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated. | 08-23-2012 |
20120286363 | Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices - A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion. | 11-15-2012 |
20120286374 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 11-15-2012 |
20130032886 | Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET - A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 02-07-2013 |
20130034940 | Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET - A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 02-07-2013 |
20130087856 | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate - A CMOS structure is formed on a semiconductor substrate that includes first and second regions having an nFET and a pFET respectively formed thereon. Each nFET and pFET device is provided with a gate, a source and drain, and a channel formed on the substrate. A high permittivity dielectric layer formed on top of the channel is superimposed to the permittivity dielectric layer. The pFET gate includes a thick metal nitride alloy layer or rich metal nitride alloy or carbon metal nitride layer that provides a controlled WF. Superimposed to the permittivity dielectric layer, the nFET gate is provided with a thin metal nitride alloy layer, enabling to control the WF. A metal deposition is formed on top of the respective nitride layers. The gate last approach characterized by having a high thermal budget smaller than 500° C. used for post metal deposition, following the dopant activation anneal. | 04-11-2013 |
20130105879 | NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE | 05-02-2013 |
20130119473 | GATE STRUCTURES AND METHODS OF MANUFACTURE - A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material. | 05-16-2013 |
20130161764 | REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE - Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly. | 06-27-2013 |
20130168776 | Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 07-04-2013 |
20130175635 | REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL - A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. | 07-11-2013 |
20130175642 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 07-11-2013 |
20130187239 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor structure including a scaled nFET and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N | 07-25-2013 |
20130193522 | REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT - The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures. | 08-01-2013 |
20130217219 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. | 08-22-2013 |
20130256802 | Replacement Gate With Reduced Gate Leakage Current - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 10-03-2013 |
20130260549 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 10-03-2013 |
20130277764 | Etch Stop Layer Formation In Metal Gate Process - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20130277767 | ETCH STOP LAYER FORMATION IN METAL GATE PROCESS - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20140001573 | SCAVENGING METAL STACK FOR A HIGH-K GATE DIELECTRIC | 01-02-2014 |
20140001575 | SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES | 01-02-2014 |
20140004695 | SCAVENGING METAL STACK FOR A HIGH-K GATE DIELECTRIC | 01-02-2014 |
20140057426 | NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE - A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region. | 02-27-2014 |
20140070307 | MULTI-LAYER WORK FUNCTION METAL REPLACEMENT GATE - Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride. | 03-13-2014 |
20140170844 | STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY - A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N | 06-19-2014 |
20140199828 | SCALED EQUIVALENT OXIDE THICKNESS FOR FIELD EFFECT TRANSISTOR DEVICES - A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion. | 07-17-2014 |
20140349451 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 11-27-2014 |
20150014782 | GATE STRUCTURES AND METHODS OF MANUFACTURE - A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material. | 01-15-2015 |
20150021698 | Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages - Intrinsic channels one or more intrinsic semiconductor materials are provided in a semiconductor substrate. A high dielectric constant (high-k) gate dielectric layer is formed on the intrinsic channels. A patterned diffusion barrier metallic nitride layer is formed. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one work function material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks. | 01-22-2015 |
20150021699 | FIN Field Effect Transistors Having Multiple Threshold Voltages - A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one workfunction material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks straddling the semiconductor fins. | 01-22-2015 |
20150069525 | SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES - A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers. | 03-12-2015 |
20150145062 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 05-28-2015 |
20150228747 | MULTIPLE THICKNESS GATE DIELECTRICS FOR REPLACEMENT GATE FIELD EFFECT TRANSISTORS - After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types. | 08-13-2015 |
20150228748 | MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS - A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric. | 08-13-2015 |
20150243662 | Low Threshold Voltage and Inversion Oxide Thickness Scaling for a High-K Metal Gate P-Type MOSFET - A semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 08-27-2015 |
20150255463 | METHODS AND STRUCTURE TO FORM HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL - A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate. | 09-10-2015 |
20150279744 | ANNEALING OXIDE GATE DIELECTRIC LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS - A method of manufacturing a semiconductor structure by forming an oxide layer above a substrate; optionally annealing the oxide layer to densify the oxide layer; forming a first sacrificial gate above the substrate; removing the first dummy gate; optionally annealing the first gate oxide layer; and forming a first replacement metal gate above the gate oxide layer. In some embodiments selective nitridation may be performed during the annealing step. | 10-01-2015 |
20150349076 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 12-03-2015 |
20150380438 | TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation. | 12-31-2015 |
20160005831 | FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS - Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions. | 01-07-2016 |
20160027664 | METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tiny (inverse of gate capacitance) mismatch. | 01-28-2016 |
20160027893 | MULTIPLE THICKNESS GATE DIELECTRICS FOR REPLACEMENT GATE FIELD EFFECT TRANSISTORS - After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types. | 01-28-2016 |
20160035841 | MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS - A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric. | 02-04-2016 |
20160049337 | METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch. | 02-18-2016 |
20160086860 | METHODS FOR MAKING ROBUST REPLACEMENT METAL GATES AND MULTI-THRESHOLD DEVICES IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer. | 03-24-2016 |
20160104707 | METHOD AND STRUCTURE FOR TRANSISTORS USING GATE STACK DOPANTS WITH MINIMAL NITROGEN PENETRATION - Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer. | 04-14-2016 |