Patent application number | Description | Published |
20130314447 | Method and Apparatus for Display Calibration - A calibration system may be provided for calibrating displays in electronic devices during manufacturing. The calibration system may include calibration computing equipment and a test chamber having a light sensor. The calibration computing equipment may be configured to operate the light sensor and the display to gather display intensity performance data for obtaining a display gamma model. The display intensity performance data may be gathered using a range of display control settings that will be used in performing color calibration operations for the display. The calibration computing equipment may be configured to operate the light sensor and the display to gather display color performance data for determining a display white point calibration. Display white point calibration data may be provided to the electronic device and stored in volatile or non-volatile memory in the device or may be permanently stored in circuitry associated with the display. | 11-28-2013 |
20140028858 | Displays and Temperature Adaptive Display Calibration - A calibration system may be provided for calibrating displays in electronic devices during manufacturing. The calibration system may include calibration computing equipment and a test chamber having a light sensor. The calibration computing equipment may be configured to operate the light sensor and the display to gather display white point information such as the native white point of the display. Temperature data may be gathered from the electronic device during display calibration operations using a thermal sensor. The calibration computing equipment may determine a temperature adaptive target white point based on the gathered temperature data. The calibration computing equipment may be configured to compare the native white point of the display with the temperature adaptive target point. Based on the comparison, the calibration computing equipment may generate corresponding display calibration parameters. The display calibration parameters may be provided to and stored in the electronic device. | 01-30-2014 |
20140071177 | SUBTRACTIVE COLOR BASED DISPLAY WHITE POINT CALIBRATION - Systems, methods, and devices for white point calibration using subtractive color measurements are provided. Specifically, a white point of a display may be calibrated using subtractive color measurements rather than merely additive color measurements. In one example, a display having red, green, and blue pixels may measure the responses in a subtractive color space (e.g., CMY) rather than additive color space (e.g., RGB). Measurements of the display response using subtractive color space may involve providing image data to two or more color channels at once. Thus, any crosstalk effect between channels may be accounted for, even though the same crosstalk effect might not be apparent using additive color measurements in which only a single channel color channel were measured. | 03-13-2014 |
20150371605 | Pixel Mapping and Rendering Methods for Displays with White Subpixels - An electronic device may include a display having an array of display pixels. The display pixels may include red, green, blue, and white subpixels. Pixel mapping circuitry may convert red-green-blue pixel values in a frame of display data to red-green-blue-white pixel values using a brightness adjustment factor. The brightness adjustment factor may be determined based on ambient lighting conditions. The brightness adjustment factor be determined such that any color distortion resulting from applying the brightness adjustment factor is maintained under a just-noticeable-difference (JND) threshold. White subpixel values may be determined based on the brightness adjustment factor. Pixel rendering circuitry may be used to render red-green-blue-white pixel values onto the physical pixel structure. When a display pixel does not include a subpixel of a particular color, the pixel rendering circuitry may compensate for the missing color using nearby subpixels. | 12-24-2015 |
Patent application number | Description | Published |
20120070589 | CREATION OF MAGNETIC FIELD (VECTOR POTENTIAL) WELL FOR IMPROVED PLASMA DEPOSITION AND RESPUTTERING UNIFORMITY - A physical vapor deposition (PVD) system includes a chamber and a target arranged in a target region of the chamber. A pedestal has a surface for supporting a substrate and is arranged in a substrate region of the chamber. A transfer region is located between the target region and the substrate region. N coaxial coils are arranged in a first plane parallel to the surface of the pedestal and below the pedestal. M coaxial coils are arranged adjacent to the pedestal. N currents flow in a first direction in the N coaxial coils, respectively, and M currents flow in a second direction in the M coaxial coils that is opposite to the first direction, respectively. | 03-22-2012 |
20120152896 | HIGH DENSITY PLASMA ETCHBACK PROCESS FOR ADVANCED METALLIZATION APPLICATIONS - A physical vapor deposition (PVD) system and method includes a chamber including a target and a pedestal supporting a substrate. A target bias device supplies DC power to the target during etching of the substrate. The DC power is greater than or equal to 8 kW. A magnetic field generating device, including electromagnetic coils and/or permanent magnets, creates a magnetic field in a chamber of the PVD system during etching of the substrate. A radio frequency (RF) bias device supplies an RF bias to the pedestal during etching of the substrate. The RF bias is less than or equal to 120V at a predetermined frequency. A magnetic field produced in the target is at least 100 Gauss inside of the target. | 06-21-2012 |
20120228125 | CREATION OF MAGNETIC FIELD (VECTOR POTENTIAL) WELL FOR IMPROVED PLASMA DEPOSITION AND RESPUTTERING UNIFORMITY - A physical vapor deposition (PVD) system includes N coaxial coils arranged in a first plane parallel to a substrate-supporting surface of a pedestal in a chamber of a PVD system and below the pedestal. M coaxial coils are arranged adjacent to the pedestal. Plasma is created in the chamber. A magnetic field well is created above a substrate by supplying N currents to the N coaxial coils, respectively, and M currents to the M coaxial coils, respectively. The N currents flow in a first direction in the N coaxial coils and the M second currents flow in a second direction in the M coaxial coils that is opposite to the first direction. A recessed feature on the substrate arranged on the pedestal is filled with a metal-containing material by PVD using at least one operation with high density plasma having a fractional ionization of metal greater than 30%. | 09-13-2012 |
20130206725 | CREATION OF OFF-AXIS NULL MAGNETIC FIELD LOCUS FOR IMPROVED UNIFORMITY IN PLASMA DEPOSITION AND ETCHING - Disclosed are methods and associated apparatus for depositing layers of material on a substrate (e.g., a semiconductor substrate) using ionized physical vapor deposition (iPVD). Also disclosed are methods and associated apparatus for plasma etching (e.g., resputtering) layers of material on a semiconductor substrate. | 08-15-2013 |
20130260057 | CONTINUOUS PLASMA AND RF BIAS TO REGULATE DAMAGE IN A SUBSTRATE PROCESSING SYSTEM - Systems and methods include supplying process gas to a processing chamber including a substrate. Plasma is created in the processing chamber. After performing a first substrate processing step, the plasma is maintained in the processing chamber and at least one operating parameter is adjusted. The operating parameters may include RF bias to a pedestal, a plasma voltage bias, a gas admixture, a gas flow, a gas pressure, an etch to deposition (E/D) ratio and/or combinations thereof. One or more additional substrate processing steps are performed without an interruption in the plasma between the first substrate processing step and the one or more additional substrate processing steps. | 10-03-2013 |
20140127912 | PLASMA PROCESS ETCH-TO-DEPOSITION RATIO MODULATION VIA GROUND SURFACE DESIGN - Plasma deposition in which properties of a discharge plasma are controlled by modifying the grounding path of the plasma is potentially applicable in any plasma deposition environment, but finds particular use in ionized physical vapor deposition (iPVD) gapfill applications. Plasma flux ion energy and E/D ratio can be controlled by modifying the grounding path (grounding surface's location, shape and/or area). Control of plasma properties in this way can reduce or eliminate reliance on conventional costly and complicated RF systems for plasma control. For a high density plasma source, the ionization fraction and ion energy can be high enough that self-sputtering may occur even without any RF bias. And unlike RF induced sputtering, self-sputtering has narrow ion energy distribution, which provides better process controllability and larger process window for integration. | 05-08-2014 |
20150294906 | METHODS FOR FORMING METAL ORGANIC TUNGSTEN FOR MIDDLE OF THE LINE (MOL) APPLICATIONS - Methods for forming metal organic tungsten for middle-of-the-line (MOL) applications are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate to a process chamber, wherein the substrate includes a feature formed in a first surface of a dielectric layer of the substrate; exposing the substrate to a plasma formed from a first gas comprising a metal organic tungsten precursor to form a tungsten barrier layer atop the dielectric layer and within the feature, wherein a temperature of the process chamber during formation of the tungsten barrier layer is less than about 225 degrees Celsius; and depositing a tungsten fill layer over the tungsten barrier layer to fill the feature to the first surface. | 10-15-2015 |
Patent application number | Description | Published |
20100199154 | Reduced processing in high-speed Reed-Solomon decoding - Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift. | 08-05-2010 |
20100287451 | Incremental generation of polynomials for decoding reed-solomon codes - An error locator polynomial is incrementally generated by flipping a bit pattern Y | 11-11-2010 |
20110078543 | PARALLEL INVERSIONLESS ERROR AND ERASURE PROCESSING - A complementary error evaluator polynomial is generated by obtaining a syndrome polynomial and one or more erasure locations. The syndrome polynomial and the erasure locations are associated with Reed-Solomon encoded information. A complementary error evaluator polynomial and an error locator polynomial are simultaneously generated using the syndrome polynomial and the erasure locations where the complementary error evaluator polynomial is a complement of the error evaluator polynomial. | 03-31-2011 |
20120131423 | BINARY BCH DECODERS - Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (Ω)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (Ω)} | 05-24-2012 |
Patent application number | Description | Published |
20080266926 | TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES - Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit. | 10-30-2008 |
20090045445 | CAPACITOR STRUCTURE USED FOR FLASH MEMORY - A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well. | 02-19-2009 |
20090147587 | CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE - Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass. | 06-11-2009 |
Patent application number | Description | Published |
20080229373 | DIGITAL VIDEO RECORDER, DIGITAL VIDEO SYSTEM, AND VIDEO PLAYBACK METHOD THEREOF - Disclosed is a digital recording apparatus, which includes: a storage device; a processing circuit, coupled to the storage device, for receiving a video signal and storing the video signal to the storage device in the form of a plurality of video files, and for generating an index data structure comprising a plurality of entries corresponding to the video files respectively; and a displaying device, coupled to the processing circuit, for displaying a video concept of the video files; wherein the processing circuit searches and compares the index data structure according to a time counting value when displaying the video concept to determine a first video file to be read of the video files and a first location of the first video file. | 09-18-2008 |
20090171886 | FILE MANAGEMENT METHOD OF A RING BUFFER AND RELATED FILE MANAGEMENT APPARATUS - A file management method of a ring buffer includes translating actual positions of an actual file stored in the ring buffer into virtual positions of a virtual file according to a specific mapping manner, searching the actual positions in the actual file according to the virtual positions, and accessing data at the actual positions of the actual file stored in the ring buffer. | 07-02-2009 |
20090204630 | DIGITAL VIDEO APPARATUS AND RELATED METHOD FOR GENERATING INDEX INFORMATION - A digital video apparatus includes a media receiver, a first storage device, and an index information generating module. The media receiver is used for receiving a media stream. The first storage device is coupled to the media receiver for storing the media stream received by the media receiver. The index information generating module is coupled to the media receiver for sequentially indexing the media stream to generate index information. | 08-13-2009 |
Patent application number | Description | Published |
20100195489 | INTERFACE MONITORING FOR LINK AGGREGATION - The present invention provides network interface monitoring and management that may be employed with link aggregation technologies. Multiple network interfaces may be aggregated into a single bond and data may be transferred to and from a backbone network via this aggregated bond. A link aggregation monitor employs a heartbeat generator, sniffer and data store to keep track of health and availability of network interfaces. The heartbeat generator sends heartbeats to the network interfaces, which pass the heartbeats around in a token ring configuration. If a network interface fails or otherwise goes offline, detection of this condition causes the monitor and heartbeat generator to prepare new or modified heartbeats so that data may be efficiently and accurately routed around the token ring and health of all remaining alive interfaces can be monitored properly. If a network interface re-enters or is added to the aggregate bond, new/modified heartbeats are then employed. | 08-05-2010 |
20110026520 | SYSTEM AND METHOD FOR IDENTIFYING MULTIPLE PATHS BETWEEN NETWORK NODES - Aspects of the invention pertain to transmitting packet data across a computer network. The packets may be sent via one or more distinct routes from a source to a destination. Each route may employ multiple routers disposed along the network. Non-colliding routes are determined by transmitting pairs of probe packets along the routes. A first probe packet has a maximal length, and a second probe packet has a minimal length. Depending on the order of arrival of the probe packets, the system determines whether two transport layer ports at the destination device collide. If there is a collision, then the system searches for a set of non-colliding ports. Once the non-colliding ports are determined, application data may be sent as packets along the different routes to those ports. | 02-03-2011 |
20110038255 | SYSTEM AND METHOD FOR GRACEFUL RESTART - A system for maintaining routing capabilities in a router having a failed control plane provides an active control plane in the router in communication with at least one external node, the active control plane running at least one routing process. A backup control plane may be interconnected with the active control plane, so that the active control plane may periodically transmit synchronization signals to the backup control plane. The backup control plane may update its state based on these synchronization signals. Moreover, the backup control plane may be programmed to take over the routing process of the active control plane if the active control plane fails. | 02-17-2011 |
20110205931 | SYSTEM AND METHOD FOR MANAGING FLOW OF PACKETS - A method for managing flow of packets comprises inputting a plurality of flow rules of various priorities to a router having a plurality of hardware resources, the plurality of hardware resources having varying levels of capability relative to each other. A first rule, for example a rule having a lowest priority, may be selected from among the plurality of flow rules, and it may be determined whether the first rule conflicts with any lower priority rules stored in the hardware resource with a highest capability. If the first rule conflicts with a lower priority rule in the hardware resource with the highest capability, the first rule may be stored in the resource with the highest capability. If the first rule does not conflict with a lower priority rule in the hardware resource with the highest capability, the first rule may be processed to identify the hardware resource with a lowest capability that can support the first rule, and the first rule may be stored in the identified resource. | 08-25-2011 |
20110299552 | SYSTEM AND METHOD FOR IDENTIFYING MULTIPLE PATHS BETWEEN NETWORK NODES - Aspects of the invention pertain to transmitting packet data across a computer network. The packets may be sent via one or more distinct routes from a source to a destination. Each route may employ multiple routers disposed along the network. Non-colliding routes are determined by transmitting pairs of probe packets along the routes. A first probe packet has a maximal length, and a second probe packet has a minimal length. Depending on the order of arrival of the probe packets, the system determines whether two transport layer ports at the destination device collide. If there is a collision, then the system searches for a set of non-colliding ports. Once the non-colliding ports are determined, application data may be sent as packets along the different routes to those ports. | 12-08-2011 |
20120014247 | INTERFACE MONITORING FOR LINK AGGREGATION - The present invention provides network interface monitoring and management that may be employed with link aggregation technologies. Multiple network interfaces may be aggregated into a single bond and data may be transferred to and from a backbone network via this aggregated bond. A link aggregation monitor employs a heartbeat generator, sniffer and data store to keep track of health and availability of network interfaces. The heartbeat generator sends heartbeats to the network interfaces, which pass the heartbeats around in a token ring configuration. If a network interface fails or otherwise goes offline, detection of this condition causes the monitor and heartbeat generator to prepare new or modified heartbeats so that data may be efficiently and accurately routed around the token ring and health of all remaining alive interfaces can be monitored properly. If a network interface re-enters or is added to the aggregate bond, new/modified heartbeats are then employed. | 01-19-2012 |
20120140616 | SYSTEM AND METHOD FOR GRACEFUL RESTART - A system for maintaining routing capabilities in a router having a failed control plane provides an active control plane in the router in communication with at least one external node, the active control plane running at least one routing process. A backup control plane may be interconnected with the active control plane, so that the active control plane may periodically transmit synchronization signals to the backup control plane. The backup control plane may update its state based on these synchronization signals. Moreover, the backup control plane may be programmed to take over the routing process of the active control plane if the active control plane fails. | 06-07-2012 |
20130169742 | VIDEO CONFERENCING WITH UNLIMITED DYNAMIC ACTIVE PARTICIPANTS - In general, this disclosure describes techniques for providing dynamic active participants in a real-time visual communication session between two or more participants. When there are more participants in the real-time visual communication session than computing devices connected to the communication session can support visual data from, a subset of the participants are chosen to be active participants. Visual data of the active participants are displayed by one or more of the computing devices. The active participants are chosen based on participation properties. Active participants may become passive and passive participants may become active based on the participation properties. The quality of visual data associated with active participants (e.g., compression rate, output display size, etc.) may be iteratively reduced as one or more of the passive participants become active. | 07-04-2013 |
20130215766 | SYSTEM AND METHOD FOR IDENTIFYING MULTIPLE PATHS BETWEEN NETWORK NODES - Aspects of the invention pertain to transmitting packet data across a computer network. The packets may be sent via one or more distinct routes from a source to a destination. Each route may employ multiple routers disposed along the network. Non-colliding routes are determined by transmitting pairs of probe packets along the routes. A first probe packet has a maximal length, and a second probe packet has a minimal length. Depending on the order of arrival of the probe packets, the system determines whether two transport layer ports at the destination device collide. If there is a collision, then the system searches for a set of non-colliding ports. Once the non-colliding ports are determined, application data may be sent as packets along the different routes to those ports. | 08-22-2013 |
20140105023 | System and Method for Assigning Paths for Data Flows Through a Wide-Area Network - A method includes, receiving a plurality of data flows. A respective data flow includes a respective source address and a respective destination address. The method further includes generating, without regard to priorities associated with the plurality of data flows, an ordering of the plurality of data flows; and iteratively modifying, without regard to the priorities, the ordering of the plurality of data flows by applying a randomization algorithm to the plurality of data flows, until a cost associated with path assignments for the ordering of the plurality of data flows satisfies a predetermined condition. A respective path assignment for a respective data flow specifies a respective path from a respective source address to a respective destination address. The method also includes executing the data flows based on the path assignments for the ordering of the plurality of data flows having the cost that satisfies the predetermined condition. | 04-17-2014 |
20150200863 | SYSTEM AND METHOD FOR UPDATING TIMESTAMPS IN LOG DATA - A system and method for updating timestamps in log data is provided. The log data is accessed to obtain timestamps corresponding to communication between a client device and a server. The timestamps include a first client timestamp corresponding to a time that the client device sends a request to the server, a first server timestamp corresponding a time the that the server receives the request from the client device, a second server timestamp corresponding to a time that the server sends a response to the request to the client device, and a second client stamp corresponding to a time that the client device receives the response from the server. A clock skew between the client device and the server and a network delay are calculated. At least one of the timestamps is updated based on the calculated clock skew and the network delay. | 07-16-2015 |
Patent application number | Description | Published |
20080204097 | INVERTER BASED DUTY CYCLE CORRECTION APPARATUSES AND SYSTEMS - Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits. | 08-28-2008 |
20080218254 | Reduced jitter amplification methods and apparatuses - Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier. | 09-11-2008 |
20090245416 | INPUT/OUTPUT DRIVER SWING CONTROL AND SUPPLY NOISE REJECTION - In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter. | 10-01-2009 |