Patent application number | Description | Published |
20080262984 | Field-Programmable Gate Array Based Accelerator System - Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm. | 10-23-2008 |
20090001941 | Inductive Powering Surface for Powering Portable Devices - Systems and methods for an inductive powering surface for powering portable devices are described. In one aspect, a powering device includes the inductive powering surface. The inductive powering surface includes multiple primary coils, an impedance auto-match circuit and other control circuits. The impedance auto-match circuit selectively energizes the primary coils to transfer power via inductive coupling to the secondary coil(s) in a portable device. The impedance auto-match circuit is configured to detect voltage and current phase differences over caused by positioning of the portable device on the inductive powering surface. The impedance auto-match circuit calibrates a power factor of the inductive powering surface to transfer an objectively maximized power load via inductive coupling to the portable device. | 01-01-2009 |
20090009469 | Multi-Axis Motion-Based Remote Control - Motion-based control of an electronic device uses an array of at least three reference elements forming a triangle. An image sensor (e.g., a video camera), which may be located on a user-manipulated device, captures an image of the array. The array image has a pattern formed by a nonparallel projection of the reference triangle onto the image sensor. The pattern carries information of the relative position between the image sensor and the reference element array, and changes as the relative position changes. The pattern is identified and used for generating position information, which may express a multidimensional position of the user-manipulated device with respect to three axes describing a translational position, and three rotational axes describing pitch, roll and yaw motions. The control system and method are particularly suitable for videogames. | 01-08-2009 |
20100067789 | RECONSTRUCTION OF IMAGE IN A BAYER PATTERN - Architecture for decoding (demosaicing) a source image and performing reconstruction directly from the Bayer pattern to reduce memory size and improve communication bandwidth. The architecture can be easily implemented in hardware such as in field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). | 03-18-2010 |
20100076911 | Automated Feature Selection Based on Rankboost for Ranking - A method using a RankBoost-based algorithm to automatically select features for further ranking model training is provided. The method reiteratively applies a set of ranking candidates to a training data set comprising a plurality of ranking objects having a known pairwise ranking order. Each round of iteration applies a weight distribution of ranking object pairs, yields a ranking result by each ranking candidate, identifies a favored ranking candidate for the round based on the ranking results, and updates the weight distribution to be used in next iteration round by increasing weights of ranking object pairs that are poorly ranked by the favored ranking candidate. The method then infers a target feature set from the favored ranking candidates identified in the iterations. | 03-25-2010 |
20100076915 | Field-Programmable Gate Array Based Accelerator System - Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and processing speed. A Field Programmable Gate Array (FPGA) is configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a Web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to Web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA. | 03-25-2010 |
20100201808 | CAMERA BASED MOTION SENSING SYSTEM - Providing camera based motion detection is disclosed herein. A camera may track a reference element array of retroreflectors, which reflect light from a light source located proximate the camera. A known arrangement of the reference element array may be compared to a received arrangement on an image sensor of the camera to determine position information of at least one of the camera or the reference element array. The reference elements may include a style (pattern, shape) that may enable extraction of additional position information when the reference element array is captured by the camera. A user-manipulated device may be configured with the camera and light source, or alternatively, the reference elements, to enable communication with a computing device and display device. | 08-12-2010 |
20110298708 | Virtual Touch Interface - A user may issue commands to a computing device by moving a pointer within a light field. Sensors may capture light reflected from the moving pointer. A virtual touch engine may analyze the reflected light captured as light portions in a sequence of images by the sensors to issue a command to a computing device in response to the movements. Analyzing the sequence of images may include finding the light portions in the sequence of images, determining a size of the light portions, and determining a location of the light portions. | 12-08-2011 |
20110300940 | Generating Position Information Using a Video Camera - Some implementations provide techniques and arrangements to receive image information. A plurality of reference fields of a user-manipulated device may be identified. Each reference field of the plurality of reference fields may include reference elements. The plurality of reference fields may be identified based on colors of the reference elements, shapes of the reference elements, and/or a pattern of the reference elements. Some implementations may generate position information based on the plurality of reference fields. The position information may identify a position of the user-manipulated device relative to the video camera. Some implementations may provide the position information to an application. | 12-08-2011 |
20110317399 | DISPLAY BACKLIGHTS WITH ADJUSTABLE NARROW VIEWING ANGLE - Display components (e.g., liquid crystal displays (LCDs)) are viewable at different viewing angles, such as by a first user positioned directly in front of the display and by a second user positioned to one side of the display. Many displays present a consistent display across a wide range of viewing angles, but these displays may consume energy and/or compromise user privacy. Presented herein are configurations of backlights for display devices featuring an adjustable viewing angle, such that a user may select a narrower viewing angle in usage scenarios involving power consumption or privacy, and may select a wider viewing angle in usage scenarios involving plentiful power and fewer privacy concerns. Such configurations may include multiple banks of backlight lamps generating backlight at different viewing angles; an electrowetting electrode as an adjustable collimator; adjustable diffusers that may adjustably scatter light passing therethrough; and/or a combination of such adjustable elements. | 12-29-2011 |
20110320405 | DETACHABLE COMPUTER WITH VARIABLE PERFORMANCE COMPUTING ENVIRONMENT - Computing devices are often designed in view of a particular usage scenario, but may be unsuitable for usage in other computing scenarios. For example, a notebook computer with a large display, an integrated keyboard, and a high-performance processor suitable for many computing tasks may be heavy, large, and power-inefficient; and a tablet lacking a keyboard and incorporating a low-powered processor may improve portability but may present inadequate performance for many tasks. Presented herein is a configuration of a computing device featuring a display unit with a resource-conserving processor that may be used independently (e.g., as a tablet), but that may be connected to a base unit featuring a resource-intensive processor. The operating system of the device may accordingly transition between a resource-intensive computing environment and a resource-conserving computing environment based on the connection with the base unit, thereby satisfying the dual roles of workstation and portable tablet device. | 12-29-2011 |
20120092040 | Field-Programmable Gate Array Based Accelerator System - Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm. | 04-19-2012 |
20120117008 | Parallel Processing Of Data Sets - Systems, methods, and devices are described for implementing learning algorithms on data sets. A data set may be partitioned into a plurality of data partitions that may be distributed to two or more processors, such as a graphics processing unit. The data partitions may be processed in parallel by each of the processors to determine local counts associated with the data partitions. The local counts may then be aggregated to form a global count that reflects the local counts for the data set. The partitioning may be performed by a data partition algorithm and the processing and the aggregating may be performed by a parallel collapsed Gibbs sampling (CGS) algorithm and/or a parallel collapsed variational Bayesian (CVB) algorithm. In addition, the CGS and/or the CVB algorithms may be associated with the data partition algorithm and may be parallelized to train a latent Dirichlet allocation model. | 05-10-2012 |
20120244910 | FLEXIBLE MOBILE DISPLAY - In general, a “Flexible Mobile Display,” as described herein, provides various techniques for implementing a flexible display for mobile phones or other handheld or portable electronic or computing devices that, in various embodiments, is foldable and/or rollable. Consequently, the Flexible Mobile Display provides a large display in a small form factor that is user extensible. Advantageously, production of the Flexible Mobile Display uses an adaptation of various currently available production techniques and is expected to be relatively low cost to produce. Additionally, in various embodiments, the Flexible Mobile Display also includes a low cost touch or multi-touch sensing mechanism that can be easily integrated into the overall system. | 09-27-2012 |
20130013587 | INCREMENTAL COMPUTING FOR WEB SEARCH - Architecture that performs incremental computing for web searches by employing methods at least for storing the results of repeat queries on unchanged webpages and for computing results for the repeated queries. The architecture includes one or more algorithms for pre-computing query results on index servers, for only selectively choosing index servers whose result for a query change for a query computation process, and for re-using the unchanged web pages stored in the cache and computing results upon changed index and unchanged index separately. | 01-10-2013 |
20130054566 | ACCELERATION OF RANKING ALGORITHMS USING A GRAPHICS PROCESSING UNIT - Methods, computer systems, and computer-readable media for accelerating a learning-to-rank algorithm using a central processing unit (CPU) and a graphics processing unit (GPU) are provided. The GPU processes document pairs created by the CPU in parallel to generate a lambda-gradient value and a weight for each document. The CPU builds a regression tree for the documents. The GPU is utilized to accelerate this process by constructing histograms of feature values, wherein the address of bins collecting the same feature value are shifted during the construction of the histogram. The output of the regression tree is a score for each document which is used to rank or order the document on a search engine results page. | 02-28-2013 |
20140141887 | GENERATING POSITION INFORMATION USING A VIDEO CAMERA - Some implementations may receive image information from a video camera and receive supplemental positioning information from a sensor of a user-manipulated device. The supplemental positioning information may be used to compensate for blind spots in the image information received from the video camera. Position information based at least in part on the image information and the supplemental positioning information may be generated. The position information may express a position and/or orientation of the user-manipulated device relative to the video camera. An application may be controlled using the generated position information. | 05-22-2014 |
Patent application number | Description | Published |
20080285770 | SERIALLY CONNECTED MICROPHONES - The invention provides a microphone. The microphone receives a first sound signal and at least one second electrical signal and outputs a third electrical signal. In one embodiment, the microphone comprises a transducer and a signal processor. The transducer converts the first sound signal to a first electrical signal. The signal processor has a first input terminal receiving the first electrical signal and at least one second input terminal receiving the at least one second electrical signal, and derives the third electrical signal from the first electrical signal and the second electrical signal. In one embodiment, the at least one second electrical signal is derived from a t least one second sound signal by at least one second microphone located in the vicinity of the microphone. In another embodiment, the at least one second electrical signal comprises a wind noise signal derived from wind pressure by a pressure sensor located in the vicinity of the microphone. | 11-20-2008 |
20080285776 | AUDIO INTERFACE DEVICE AND METHOD - The invention provides an audio interface device and method to acquire audio signal from either an analog or digital microphone through a common connector. The audio interface comprises a connector, electrically connected with a microphone plugged thereinto, an analog readout circuit, acquiring an analog audio signal from an analog microphone, a digital readout circuit, acquiring a digital audio signal from a digital microphone, and a decision circuit, selectively connecting the analog or digital readout circuit to the connector to acquire the analog or digital audio signal respectively according to whether the microphone plugged into the connector is analog or digital. | 11-20-2008 |
20080298607 | AUDIO INTERFACE DEVICE AND METHOD - The invention provides an audio interface device and method utilizing a single audio jack connector for plugging into a three-wire analog microphone or a three-wire digital microphone, thereby reducing dimensions and production costs thereof and an electronic system using the same. The audio interface comprises an audio jack connector, having first to third contacts electronically connected with the three-wire microphone plugged thereinto; and an audio processing device, detecting a type of the three-wire microphone plugged into the audio jack connector, outputting a clock signal to the three-wire microphone and receiving a digital audio signal from the three-wire microphone when the type is digital; or receiving analog audio signals from the three-wire microphone when the type is analog. | 12-04-2008 |
20090086992 | MICROPHONE CIRCUIT AND CHARGE AMPLIFIER THEREOF - The invention provides a microphone circuit. In one embodiment, the microphone circuit comprises a microphone, a self-biased amplifier with a finite gain, and a feedback capacitor. The microphone coupled between a ground and a first node generates a first voltage at the first node according to sound pressure. The self-biased amplifier has a positive input terminal coupled to the ground and a negative input terminal coupled to the first node and amplifies the first voltage according to the finite gain to generate a second voltage at a second node. The feedback capacitor coupled between the first node and the second node feeds back the second voltage to the first node. The second voltage is then output to a following module subsequent to the microphone circuit. | 04-02-2009 |
20090323980 | ARRAY MICROPHONE SYSTEM AND A METHOD THEREOF - An array microphone system of compensating phase drift of input signals and a method thereof. The microphone system comprises a speaker, first and second microphones, a delay estimator, and a memory. The speaker outputs an acoustic signal. The first and second microphones, spaced by a predetermined distance, receive the acoustic signal to generate first and second input signals. The delay estimator, coupled to the first and second microphones, computes a time difference between the first and second input signals. The memory, coupled to the delay estimator, stores the time difference. | 12-31-2009 |
20100027830 | CHIP-SCALED MEMS MICROPHONE PACKAGE - An MEMS microphone package includes a circuit board and an MEMS microphone chip. The MEMS microphone chip, mounted on the circuit board, includes a substrate, an MEMS transducer formed on the substrate, and a readout circuit also formed on the substrate. The MEMS transducer generates a sound signal according to sound pressure variations. The readout circuit reads the sound signal from the MEMS transducer. | 02-04-2010 |
20100086146 | SILICON-BASED MICROPHONE PACKAGE - A microphone package includes a carrier, a cap, a first silicon-based microphone, and a first integrated circuit chip. The carrier has a first storage space. The cap has a planar part contacting the carrier and a plurality of flanges extending from the planar part and surrounding the carrier. The first silicon-based microphone is disposed in the first storage space and covered by the cap. The first integrated circuit chip is disposed in the first storage space, electrically connected to the first silicon-based microphone, and covered by the cap. | 04-08-2010 |
20100086164 | MICROPHONE PACKAGE WITH MINIMUM FOOTPRINT SIZE AND THICKNESS - A microphone package includes a carrier, a cap, an integrated circuit chip, and a microphone unit. The cap covers the carrier to form a storage space. The integrated circuit chip is disposed in the storage space. The microphone unit is disposed in the storage space and stacked on the integrated circuit chip. | 04-08-2010 |
20120163634 | AUDIO INTERFACE DEVICE AND METHOD - The invention provides an audio interface device and method utilizing a single audio jack connector for plugging into a three-wire analog microphone or a three-wire digital microphone, thereby reducing dimensions and production costs thereof and an electronic system using the same. The audio interface comprises an audio jack connector, having first to third contacts electronically connected with the three-wire microphone plugged thereinto; and an audio processing device, detecting a type of the three-wire microphone plugged into the audio jack connector, outputting a clock signal to the three-wire microphone and receiving a digital audio signal from the three-wire microphone when the type is digital; or receiving analog audio signals from the three-wire microphone when the type is analog. | 06-28-2012 |