Patent application number | Description | Published |
20090206867 | Self-Test Method for Interface Circuit - An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal. | 08-20-2009 |
20090238025 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 09-24-2009 |
20100039875 | Strobe Acquisition and Tracking - A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value. | 02-18-2010 |
20120188835 | INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 07-26-2012 |
20130111176 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT | 05-02-2013 |
20140140149 | Strobe Acquisition and Tracking - A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value. | 05-22-2014 |
20140173240 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 06-19-2014 |
Patent application number | Description | Published |
20090034344 | Methods and apparatus for strobe signaling and edge detection thereof - A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations. | 02-05-2009 |
20100202227 | REFERENCE VOLTAGE AND IMPEDANCE CALIBRATION IN A MULTI-MODE INTERFACE - A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through the input node. The memory controller includes a calibration circuit and control logic coupled to the calibration circuit, where the calibration circuit and the control logic are configured to select a first reference voltage and a driver impedance for the transmit circuit and are configured to select a second reference voltage and a termination impedance for the receive circuit. The first reference voltage, the second reference voltage, the driver impedance and the termination impedance are selected from a set of pre-determined values, which are associated with different signaling modes for communication of the first data and the second data. | 08-12-2010 |
20110010575 | MULTI-DROP SIGNALING SYSTEM AND METHOD EMPLOYING SOURCE TERMINATION - A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order. | 01-13-2011 |
20110249514 | METHODS AND APPARATUS FOR STROBE SIGNALING AND EDGE DETECTION THEREOF - A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations. | 10-13-2011 |
20120063524 | SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION - A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information. | 03-15-2012 |