Patent application number | Description | Published |
20080244884 | Method for Forming Ceramic Thick Film Element Arrays with Fine Feature Size, High-Precision Definition, and/or High Aspect Ratios - A method is provided that includes providing a mold on a temporary substrate, e.g., a sapphire substrate. Next, a material such as PZT paste is deposited into the mold. Then, the mold is removed to obtain elements formed by the mold. The formed elements will then be sintered. After sintering, electrode deposition is optionally performed. The sintered elements are then bonded to a final target substrate and released from the temporary substrate through laser liftoff. Further, electrodes may also be optionally deposited at this point. | 10-09-2008 |
20090047558 | MICRO-MACHINED FUEL CELLS - An improved fuel cell is described. The invention addresses the problem of mechanical failure in thin electrolytes. One embodiment varies the thickness of the electrolyte and positions at least either the anode or cathode in the recessed region to provide a short travel distance for ions traveling from the anode to the cathode or from the cathode to the anode. A second embodiment uses a uniquely shaped manifold cover to allow close positioning of the anode to the cathode. Using the described structures results in a substantial improvement in fuel cell reliability and performance. | 02-19-2009 |
20090070975 | METHOD OF FORMING MICROMACHINED FLUID EJECTORS USING PIEZOELECTRIC ACTUATION - A method of forming a fluid ejector includes forming a recess well into a silicon wafer on a first side of the silicon wafer, and filling the recess well with a sacrificial material. A thin layer structure is deposited onto the first side of a silicon wafer covering the filled recess well. Then a thin film piezoelectric is bonded or deposited to the thin layer structure, and a hole is formed in the thin layer structure exposing at least a portion of the sacrificial material. The sacrificial material is removed from the recess well, wherein the hole in the thin layer in the recess well with the sacrificial material removed, form a fluid inlet. An opening area in the silicon wafer is formed on a second side of the silicon wafer. Then a nozzle plate is formed having a recess portion and an aperture within the recess portion. The nozzle plate is attached to the second side of the silicon wafer, with the recess portion positioned within the open area. The thin layer structure and the recess portion of the nozzle plate define a depth of a fluid cavity defined by the thin layer structure, the recess portion of the nozzle plate and the sidewalls of the silicon wafer. | 03-19-2009 |
20090073242 | MULTI-LAYER MONOLITHIC FLUID EJECTORS USING PIEZOELECTRIC ACTUATION - A fluid ejector including a silicon wafer having a first side and a second side. A multi-layer monolithic structure is formed on the first side of the silicon wafer. The multi-layer monolithic structure includes a first structure layer formed on the first side of the silicon wafer, and the first structure layer has an aperture. A second structure layer has a horizontal portion and closed, filled trenches or vertical sidewalls. The first structure layer, horizontal portion and the closed, filled trenches or vertical sidewalls of the second structure layer define a fluid cavity. An actuator is associated with the horizontal portion of the second structure layer, and an etched portion of the silicon wafer defines an open area which exposes the aperture in the first structure layer. | 03-19-2009 |
Patent application number | Description | Published |
20100156997 | DROP GENERATING APPARATUS - A drop generator having a via structure configured for electrical and fluidic interconnection. The via structure includes an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer. | 06-24-2010 |
20100159193 | COMBINED ELECTRICAL AND FLUIDIC INTERCONNECT VIA STRUCTURE - A via structure configured for electrical and fluidic interconnection, and including an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer. | 06-24-2010 |
20110087717 | METHOD FOR DECIMATION OF IMAGES - In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process. | 04-14-2011 |
20110087718 | METHOD FOR DECIMATION OF IMAGES - In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process. | 04-14-2011 |
Patent application number | Description | Published |
20090128189 | Three dimensional programmable devices - In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements. | 05-21-2009 |
20110242880 | MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity. | 10-06-2011 |
20120032276 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 02-09-2012 |
20120261738 | N-Well/P-Well Strap Structures - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 10-18-2012 |