Patent application number | Description | Published |
20100027315 | Resistive memory device and writing method thereof - A resistive memory device operates to sequentially activate bit lines, which are divided into plural groups, after precharging all of word and bit lines in a writing operation. The device is able to write a large amount of data therein at a high frequency, with a reduced the chip size. | 02-04-2010 |
20100027326 | Memory device, memory system having the same, and programming method of a memory cell - A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit. | 02-04-2010 |
20100085826 | Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same - The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit. | 04-08-2010 |
20100091552 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit. | 04-15-2010 |
20100172172 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND VOLTAGE SUPPLY METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices. | 07-08-2010 |
20100172174 | SEMICONDUCTOR DEVICE HAVING ARCHITECTURE FOR REDUCING AREA AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation. | 07-08-2010 |
20100182866 | SEMICONDUCTOR MEMORY DEVICE FOR COMPENSATING FOR OPERATING VOLTAGE DIFFERENCE BETWEEN NEAR CELL AND FAR CELL IN CONSIDERATION OF CELL POSITION, AND MEMORY CARD AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into at least two local bit line groups arranged to be alternately connected with at least two global bit lines and coupled with the memory cells; a plurality of bit line selection drivers respectively connected to the local bit lines; an internal boosted voltage generator configured to generate at least two internal boosted voltages having different levels; and a power transmitter configured to respectively transmit the at least two internal boosted voltages to at least two bit line selection driver groups, into which the plurality of bit line selection drivers are classified according to arrangement of the local bit lines. Accordingly, repair efficiency can be increased and near-far compensation can be more correctly performed. | 07-22-2010 |
20100202182 | MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS - A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays. | 08-12-2010 |
20100208381 | Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal. | 08-19-2010 |
20100208504 | Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains. | 08-19-2010 |
20100214819 | RESISTIVE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF CONTROLLING INPUT AND OUTPUT OPERATIONS OF THE SAME - A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage | 08-26-2010 |
20100214831 | Memory device, memory system having the same, and programming method of a memory cell - A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data. | 08-26-2010 |
20100214862 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 08-26-2010 |
20100218073 | Resistive Memory Devices and Methods of Controlling Operations of the Same - To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc. | 08-26-2010 |
20100220513 | Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data - A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided. | 09-02-2010 |
20100223532 | SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE - A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit. | 09-02-2010 |
20100226165 | RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF - A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode. | 09-09-2010 |
20100246234 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers. | 09-30-2010 |
20100246246 | Memory device, memory system having the same, and programming method of a memory cell - A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell. | 09-30-2010 |
20100250848 | APPARATUSES AND METHODS PROVIDING REDUNDANT ARRAY OF INDEPENDENT DISKS ACCESS TO NON-VOLATILE MEMORY CHIPS - A controller may include a RAID controller and an access controller. The RAID controller exchanges data with a host and select ones of a plurality of RAID levels responsive to RAID level information. The access controller is connected to the RAID controller and to a plurality of channels that are each connected to a plurality of non-volatile memory chips. The access controller accesses data in at least one of the non-volatile memory chips connected to each of the channels according to the selected RAID level. The controller may alternatively or additionally include a storage device and a main processor. The main processor is configured to logically partition a plurality of non-volatile memory chips that are connected to each of a plurality of channels into a normal partition region and a RAID level partition region, where data access is performed according to a selected RAID level, in response partition information that is stored in the storage device. | 09-30-2010 |
20100284209 | INTEGRATED CIRCUIT MEMORY SYSTEMS AND PROGRAM METHODS THEREOF INCLUDING A MAGNETIC TRACK MEMORY ARRAY USING MAGNETIC DOMAIN WALL MOVEMENT - Provided are nonvolatile memory devices and program methods thereof. an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track. | 11-11-2010 |
20100284216 | INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME - An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data. | 11-11-2010 |
20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 12-09-2010 |
20110062448 | Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices - Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer. | 03-17-2011 |
20110063885 | Information storage devices including vertical nano wires - A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires. | 03-17-2011 |
20110085368 | Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines. | 04-14-2011 |
20110108704 | Image sensors and methods of operating the same - Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively. | 05-12-2011 |
20110128772 | Nonvolatile memory cells and nonvolatile memory devices including the same - A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor. | 06-02-2011 |
20110133778 | NON-VOLATILE LOGIC CIRCUITS, INTEGRATED CIRCUITS INCLUDING THE NON-VOLATILE LOGIC CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS - Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different. | 06-09-2011 |
20110194328 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell. | 08-11-2011 |
20110221482 | Semiconductor device - Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage. | 09-15-2011 |
20110222685 | Storage devices having a security function and methods of securing data stored in the storage device - A storage device may include a storage unit that stores data transmitted via a plurality of first wires; and a security control unit that controls connection between each of a plurality of second wires connected to an external device and each of the plurality of first wires by programming a plurality of switching devices according to an encryption key. | 09-15-2011 |
20110228585 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change. | 09-22-2011 |
20110273116 | Driving circuits, power devices and electric devices including the same - A power device includes a switching device and a control unit. The switching device has a control terminal and an output terminal. The control unit is configured to control a rising time required for a driving voltage for controlling the switching device to reach a target level such that a voltage between the control terminal and the output terminal is maintained less than or equal to a critical voltage. When the voltage between the control terminal and the output terminal is greater than the critical voltage, leakage current is generated between the control terminal and the output terminal. | 11-10-2011 |
20110273221 | Driving circuits, power devices and electronic devices including the same - A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal. | 11-10-2011 |
20110286275 | Stacked Memory Devices And Method Of Manufacturing The Same - A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings. | 11-24-2011 |
20120038428 | Oscillators and method of operating the same - Oscillators and a method of operating the same are provided, the oscillators include at least one oscillation device including a first magnetic layer having a magnetization direction that is variable, a second magnetic layer having a pinned magnetization direction, and a non-magnetic layer disposed between the first magnetic layer and the second magnetic layer. The oscillation device is configured to generate a signal having a set frequency. The oscillators further include a driving transistor having a drain connected to the at least one oscillation device, and a gate to which a control signal for controlling driving of the oscillation device is applied. | 02-16-2012 |
20120063196 | RESISTIVE MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION OF RESISTIVE MEMORY DEVICE - A resistive memory device comprises a memory cell array comprising a plurality of memory units. The memory device performs a refresh read operation to check a condition of each of the memory units. Then, it determines whether to refresh each memory unit based on data read by performing the refresh read operation, and refreshes the memory unit according to a result of the determination. The refresh read operation uses a reference resistance with a smaller margin from a resistance distribution than a normal read operation. | 03-15-2012 |
20120112796 | Oscillators and methods of operating the same - Oscillators and methods of operating the oscillators are provided, the oscillators include an oscillating unit including at least one magnetic layer having a magnetization direction that varies according to at least one selected from the group consisting of an applied current, an applied voltage and an applied magnetic field. The oscillating unit is configured to generate an oscillation signal having a set frequency. The oscillators further include an output stage that provides an output signal by differentially amplifying the oscillation signal. | 05-10-2012 |
20120133538 | RESISTOR DEVICES AND DIGITAL-TO-ANALOG CONVERTERS USING THE SAME - A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices. | 05-31-2012 |
20120140545 | SEMICONDUCTOR DEVICE AND METHOD OF SENSING DATA OF THE SEMICONDUCTOR DEVICE - In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit. | 06-07-2012 |
20120210054 | DATA STORAGE MEDIUM HAVING SECURITY FUNCTION AND OUTPUT APPARATUS THEREFOR - Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus. | 08-16-2012 |
20120212255 | Logic Circuit, Integrated Circuit Including The Logic Circuit, And Method Of Operating The Integrated Circuit - The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value. | 08-23-2012 |
20120326747 | RECONFIGURABLE LOGIC DEVICE - A logic device that includes a plurality of non-volatile memory cells configured to store possible output results related to the input signal. The logic device generating an output signal by selecting and accessing one of the plurality of non-volatile memory cells based on the input signal. | 12-27-2012 |
20130069714 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE - A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage. | 03-21-2013 |
20130121059 | MULTI-VALUED LOGIC DEVICE HAVING NONVOLATILE MEMORY DEVICE - A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal. | 05-16-2013 |
20130128683 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 05-23-2013 |
20130177323 | MICROPROCESSOR CHIP, DATA CENTER, AND COMPUTING SYSTEM - A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit. | 07-11-2013 |
20130241520 | POWER MANAGEMENT CHIPS AND POWER MANAGEMENT DEVICES INCLUDING THE SAME - A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch. | 09-19-2013 |
20130241604 | POWER MODULE INCLUDING LEAKAGE CURRENT PROTECTION CIRCUIT - A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator. | 09-19-2013 |
20130265028 | HIGH SIDE GATE DRIVER, SWITCHING CHIP, AND POWER DEVICE - A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure. | 10-10-2013 |
20140036575 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell. | 02-06-2014 |
20140050005 | NONVOLATILE MEMORY APPARATUS AND METHOD OF OPERATING THE SAME - Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array. | 02-20-2014 |
20140097404 | MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES - A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element. | 04-10-2014 |
20140125378 | LOGIC DEVICE AND OPERATING METHOD THEREOF - A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function. | 05-08-2014 |
20140140397 | LOGIC DEVICES, DIGITAL FILTERS AND VIDEO CODECS INCLUDING LOGIC DEVICES, AND METHODS OF CONTROLLING LOGIC DEVICES - A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation. | 05-22-2014 |
20140233305 | MAGNETIC RANDOM ACCESS MEMORY HAVING INCREASED ON/OFF RATIO AND METHODS OF MANUFACTURING AND OPERATING THE SAME - A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits. | 08-21-2014 |
20150028278 | NONVOLATILE MEMORY TRANSISTOR AND DEVICE INCLUDING THE SAME - Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic. | 01-29-2015 |