Patent application number | Description | Published |
20100091416 | MAGNETIC READ HEAD - A magnetoresistive head which has a high head SNR by reducing generated mag-noise without deteriorating an output comprises, according to one embodiment, a magnetoresistive sensor having a laminated structure which includes an antiferromagnetic layer, a magnetization pinned layer, a non-magnetic intermediate layer, a magnetization free layer, and a magnetization stable layer arranged adjacent to the magnetization free layer. The magnetization stable layer comprises non-magnetic coupling layer, a first ferromagnetic stable layer, an antiparallel coupling layer, and a second ferromagnetic stable layer. A magnetization quantity of a first ferromagnetic stable layer and a second ferromagnetic stable layer are substantially equal, and the magnetization of the first ferromagnetic stable layer and the second ferromagnetic stable layer are magnetically coupled in the antiparallel direction from each other. The magnetizations of the first ferromagnetic stable layer and the free layer are coupled in an antiferromagnetic or a ferromagnetic alignment. | 04-15-2010 |
20100118448 | DIFFERENTIAL HEAD HAVING A BALANCED OUTPUT AND METHOD OF MANUFACTURING THEREOF - In one embodiment, a differential-type magnetic read head includes a differential-type magneto-resistive-effect film formed on a substrate, and a pair of electrodes for applying current in a direction perpendicular to a film plane of the film. The film includes a first and second stacked film, each having a pinned layer, an intermediate layer, and a free layer, with the second stacked film being formed on the first stacked film. A side face in a track width direction of the film is shaped to have an inflection point at an intermediate position in a thickness direction of the film, and the side face is shaped to be approximately vertical to the substrate in an upward direction of the substrate from the inflection point. Also, the side face is shaped to be gradually increased in track width as approaching the substrate in a downward direction of the substrate from the inflection point. | 05-13-2010 |
20100142101 | DIFFERENTIAL MAGNETORESISTIVE EFFECT HEAD AND MAGNETIC RECORDING/READING DEVICE - According to one embodiment, a differential magnetoresistive effect element comprises a first magnetoresistive effect element having a first pinning layer, a first intermediate layer, and a first free layer. The differential magnetoresistive effect element also comprises a second magnetoresistive effect element stacked via a spacer layer above the first magnetoresistive effect element, the second magnetoresistive effect element having a second pinning layer, a second intermediate layer, and a second free layer. The first magnetoresistive effect element and the second magnetoresistive effect element show in-opposite-phase resistance change in response to a magnetic field in the same direction, and tp | 06-10-2010 |
Patent application number | Description | Published |
20100182820 | Variable resistance memory device - A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells. | 07-22-2010 |
20100195370 | Nonvolatile semiconductor memory device and method for performing verify write operation on the same - Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification. | 08-05-2010 |
20100214818 | Memory device and operation method of the same - Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a voltage applied and an access transistor connected in series between the first and second wires; driving control sections controlling a direct verify sub-operation by applying a write/erase pulse between the first and second wires in a data write/erase operation respectively for causing a cell current to flow between the first and second wires through the memory cell for a transition of the data storage state; sense amplifiers sensing an electric-potential change occurring on the first wire in accordance with control on the direct verify sub-operation; and inhibit control sections determining whether or not to inhibit a sense node of the sense amplifier from electrically changing at the next sensing time on the basis of an electric potential appearing at the sense node at the present sensing time. | 08-26-2010 |
20100254178 | STORAGE DEVICE AND INFORMATION RE-RECORDING METHOD - A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-value recording is provided. An initial value of a potential difference VCG between a gate and a source of a switching transistor at the time of the verify is set to a value varied in accordance with a resistance value level of multi-value information. In the case where a writing side performs a 3-value recording, when “01” is the information, an initial value VGS | 10-07-2010 |
20100259968 | STORAGE DEVICE AND INFORMATION RERECORDING METHOD - A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ΔVWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ΔVWL is a value variable for every resistance value level of multiple value information. That is, ΔVWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ΔVWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ΔVWL is large. | 10-14-2010 |
20110026298 | METHOD OF DRIVING STORAGE DEVICE - Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes | 02-03-2011 |
20110110142 | Memory device and method of reading memory device - A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit. | 05-12-2011 |
20110116296 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device includes: a memory component in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one of the electrodes of the memory component is connected with a reference electric potential; and a load capacitance changing unit that changes load capacitance of a sense node of the sense amplifier to which the discharge electric potential is input or both the load capacitance of the sense node and load capacitance of a reference node of the sense amplifier to which the reference electric potential is input in accordance with the logic of the information read out by the memory component. | 05-19-2011 |
20110149635 | STORAGE DEVICE AND INFORMATION RERECORDING METHOD - A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased). | 06-23-2011 |
20110199812 | Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected to the cell wiring, the sense amplifier reading the logical value of the information by comparing a potential of the sense node with a reference potential; and a readout control circuit capable of switching between a dynamic sense operation performing readout by precharging the cell wiring and discharging or charging the cell wiring via the memory element and a static sense operation performing readout in a state of a current load being connected to the sense node. | 08-18-2011 |
20110222355 | Control voltage generation circuit and nonvolatile storage device having the same - Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage. | 09-15-2011 |
20110305068 | RESISTANCE RANDOM ACCESS CHANGE MEMORY DEVICE - A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines. | 12-15-2011 |
20120212994 | MEMORY APPARATUS - A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element. | 08-23-2012 |
20120218809 | STORAGE APPARATUS AND OPERATION METHOD FOR OPERATING THE SAME - A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished. | 08-30-2012 |
20120294064 | VARIABLE-RESISTANCE MEMORY DEVICE AND ITS OPERATION METHOD - Disclosed herein is a variable-resistance memory device including a first common line; a second common line; a storage element connected between the first common line and the second common line to serve as a storage element whose resistance changes in accordance with a voltage applied to the storage element; and a driving control circuit. | 11-22-2012 |
20140022833 | STORAGE APPARATUS AND OPERATION METHOD FOR OPERATING THE SAME - A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished. | 01-23-2014 |
20140254241 | SEMICONDUCTOR DEVICE AND INFORMATION READING METHOD - A semiconductor device includes; a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states. | 09-11-2014 |