Patent application number | Description | Published |
20080244533 | System for and Method of Capturing Performance Characteristics Data From A Computer System and Modeling Target System Performance - A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered. | 10-02-2008 |
20090055594 | System for and method of capturing application characteristics data from a computer system and modeling target system - A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. | 02-26-2009 |
20090125465 | SYSTEM FOR AND METHOD OF CAPTURING APPLICATION CHARACTERISTICS DATA FROM A COMPUTER SYSTEM AND MODELING TARGET SYSTEM - A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered. | 05-14-2009 |
20150143046 | SYSTEMS AND METHODS FOR REDUCING FIRST LEVEL CACHE ENERGY BY ELIMINATING CACHE ADDRESS TAGS - Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy. | 05-21-2015 |
20150143047 | SYSTEMS AND METHODS FOR DIRECT DATA ACCESS IN MULTI-LEVEL CACHE MEMORY HIERARCHIES - Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories. | 05-21-2015 |
20150347297 | SYSTEMS AND METHODS FOR IMPLEMENTING A TAG-LESS SHARED CACHE AND A LARGER BACKING CACHE - A computer processing system includes a plurality of nodes, each node having at least one processor core and at least one level of cache memory which is private to the node, a shared, last level cache (LLC) memory device and a shared, last level cache location buffer containing cache location entries, each cache location entry storing an address tag and a plurality of location information. The location information stored in a cache location entry points to an identified cacheline location within the LLC that stores a cacheline associated with the location information. The cacheline stored in the LLC has associated information identifying the cache location entry. | 12-03-2015 |
20150347298 | TRACKING ALTERNATIVE CACHELINE PLACEMENT LOCATIONS IN A CACHE HIERARCHY - Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline. | 12-03-2015 |
20150347299 | PLACEMENT POLICY FOR MEMORY HIERARCHIES - A placement policy enables the selective storage of cachelines in a multi-level cache hierarchy: Reuse behavior of a cacheline is tracked during execution of an application in both a first level cache memory and a second level cache memory. A cache placement policy for the cacheline is determined based on the tracked reuse behavior. | 12-03-2015 |
20150347302 | MANAGEMENT OF SHARED PIPELINE RESOURCE USAGE BASED ON LEVEL INFORMATION - The execution or processing of an application can be adapted or modified based on a level of a cache in which a requested data block resides, by extracting level information from a cache hierarchy. When a request for a data block is made by a core to a cache memory system, the cache memory system extracts a level of a cache memory in which the data block resides from information stored in the cache memory system. The core is informed of the level of the cache memory in which the data block resides, and uses this information to adapt its processing of the application. | 12-03-2015 |