Patent application number | Description | Published |
20140077718 | TWO-WIRE DIMMER WITH IMPROVED ZERO-CROSS DETECTION - A two-wire lighting control device, may include a controllably conductive device, a signal generation circuit, and a filter circuit. The controllably conductive device may apply an AC line voltage to a load, being conductive for a first duration of time and non-conductive for a second duration of time within a half-cycle of the AC line voltage. The signal generation circuit may generate a non-zero-magnitude signal. And, the filter circuit may receive a signal from the controllably conductive device during the first duration of time and the non-zero-magnitude signal from the signal generation circuit during the second duration of time. The non-zero-magnitude signal may, in effect, fill-in or complement the signal from the controllably conductive device, and any delay variation as a function of the firing angle of the controllably conductive device through the filter circuit may be mitigated by the presence of the non-zero-magnitude signal. | 03-20-2014 |
20150054471 | Electronic Switch having an In-Line Power Supply - A two-wire smart load control device, such as an electronic switch, for controlling the power delivered from a power source to an electrical load comprises a relay for conducting a load current through the load and an in-line power supply coupled in series with the relay for generating a supply voltage across a capacitor when the relay is conductive. The power supply controls when the capacitor charges asynchronously with respect to the frequency of the source. The capacitor conducts the load current for at least a portion of a line cycle of the source when the relay is conductive. The load control device also comprises a bidirectional semiconductor switch, which is controlled to minimize the inrush current conducted through the relay. The bidirectional semiconductor switch is rendered conductive in response to an over-current condition in the capacitor of the power supply, and the relay is rendered non-conductive in response to an over-temperature condition in the power supply. | 02-26-2015 |
20150373817 | TWO-WIRE DIMMER WITH IMPROVED ZERO-CROSS DETENTION - A two-wire lighting control device, may include a controllably conductive device, a signal generation circuit, and a filter circuit. The controllably conductive device may apply an AC line voltage to a load, being conductive for a first duration of time and non-conductive for a second duration of time within a half-cycle of the AC line voltage. The signal generation circuit may generate a non-zero-magnitude signal. And, the filter circuit may receive a signal from the controllably conductive device during the first duration of time and the non-zero-magnitude signal from the signal generation circuit during the second duration of time. The non-zero-magnitude signal may, in effect, fill-in or complement the signal from the controllably conductive device, and any delay variation as a function of the firing angle of the controllably conductive device through the filter circuit may be mitigated by the presence of the non-zero-magnitude signal. | 12-24-2015 |
20160070414 | Electronic Devices With Replaceable Subassemblies - An electronic device may include electrical components. The electrical components may be calibrated. Calibration data may be stored in non-volatile memory on a component assembly or may be stored in a remote databased while a subassembly identifier is stored in the non-volatile memory. If a subassembly in a device becomes damaged, a replacement subassembly may be installed in the device. Control circuitry in the device may retrieve calibration data for the replacement subassembly from non-volatile memory on the subassembly or from the remote database. | 03-10-2016 |
Patent application number | Description | Published |
20140091390 | Protection Layer for Halftone Process of Third Metal - A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor. | 04-03-2014 |
20140118666 | Display with Column Spacer Structures Resistant to Lateral Movement - A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support. Lateral movement blocking structures such as circular rings may be used to prevent column spacer lateral movement. Subspacers located over pads may be used to create friction that retards lateral movement. Lateral movement may also be retarded by receiving column spacers in trenches or other recesses formed on a thin-film transistor layer. | 05-01-2014 |
20140138637 | FLEXIBLE DISPLAY - A flexible display having an array of pixels or sub-pixels is provided. The display includes a flexible substrate and an array of thin film transistors (TFTs) corresponding to the array of pixels or sub-pixels on the substrate. The display also includes a first plurality of metal lines coupled to gate electrodes of the TFTs and a second plurality of metal lines coupled to source electrodes and drain electrodes of the TFTs. At least one of the first plurality of metal lines and the second plurality of metal lines comprises a non-stretchable portion in the TFT areas and a stretchable portion outside the TFT areas. | 05-22-2014 |
20140211120 | Third Metal Layer for Thin Film Transistor witih Reduced Defects in Liquid Crystal Display - A liquid crystal display (LCD) includes an array of pixels over a thin film transistor (TFT) substrate. The TFT substrate includes a TFT that has a first metal layer to form a gate electrode and a second metal layer to form a source electrode and a drain electrode for each pixel. The LCD also includes an organic insulation layer disposed over the TFT substrate, where the organic insulator layer has trenches on a top surface. The LCD further includes a third metal layer disposed over the organic insulation layer in the trenches, the trenches having a trench depth at least equal to the thickness of the third metal layer. The LCD also includes a passivation layer over the third metal layer, and a pixel electrode for each pixel over the passivation layer. The LCD further includes a polymer layer over the pixel electrode, and liquid molecules on the polymer layer. | 07-31-2014 |
20140240985 | Electronic Device With Reduced-Stress Flexible Display - An electronic device may have a flexible display. The display may have portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area and signal lines, thin-film transistor support circuitry and other display circuitry in an inactive area of the display surrounding the active area. The display circuitry may be formed on a substrate such as a flexible polymer substrate. The flexible polymer substrate may be formed by depositing polymer on a support structure that has raised portions. | 08-28-2014 |
20150146144 | Border Masking Structures for Liquid Crystal Display - A display may have a thin-film transistor layer and color filter layer. The display may have an active area and an inactive border area. Light blocking structures in the inactive area may prevent stray backlight from a backlight light guide plate from leaking out of the display. The thin-film transistor layer may have a clear substrate, a patterned black masking layer on the clear substrate, a clear planarization layer on the black masking layer, and a layer of thin-film transistor circuitry on the clear planarization layer. The black masking layer may be formed from black photoimageable polyimide. The clear planarization layer may be formed from spin-on glass. The light blocking structures may include a first layer formed from a portion of the black masking layer and a second layer such as a layer of black tape on the underside of the color filter layer. | 05-28-2015 |
20150219972 | Displays with Flipped Panel Structures - A display may have a thin-film transistor layer and a color filter layer. The display may include light blocking structures formed on a transparent substrate. In one arrangement, a clear planarization layer may be formed over the light blocking structures. The thin-film transistor layer may be formed over the planarization layer. The color filter layer may be integrated with the thin-film transistor layer. At least light blocking structures and the planarization layer should be formed from high temperature resistance material. In another arrangement, the color filter layer may be formed on the light blocking structures. A clear planarization layer may then be formed over the color filter layer. The thin-film transistor layer may be formed on the planarization layer. In this arrangement, the color filter layer also needs to be formed from thermal resistance material. | 08-06-2015 |
20150286106 | Border Masking Structures for Liquid Crystal Displays - A display may have a thin-film transistor (TFT) layer and color filter layer. Light blocking structures in an inactive area of the display may prevent stray backlight from leaking out of the display. The thin-film transistor layer may have a first substrate, a first black masking layer, a planarization layer, and a layer of TFT circuitry on the planarization layer. The color filter layer may have a second substrate and a second black masking layer on the second substrate. Light-cured sealant may be formed between the TFT layer and the color filter layer. Gaps may be formed in the second black masking layer to allow light to cure the sealant. At least a portion of the TFT circuitry may serve to block stray backlight penetrating through the gaps in the second black masking layer during normal operation of the display. | 10-08-2015 |
20150301417 | Logo Patterning Methods for Liquid Crystal Displays - A display may have a thin-film transistor (TFT) layer and a color filter layer. The TFT layer may have a first substrate, a first black masking layer, a planarization layer, and a layer of TFT circuitry on the planarization layer. The color filter layer may have a second substrate and a second black masking layer on the second substrate. A portion of the inactive area may serve as a logo area for displaying desired information to the user. A reflective structure may be formed on the bottom surface of the planarization layer, on the bottom surface of the first substrate, on the bottom surface of the second substrate, or on the upper surface of the first substrate in the logo area. In another embodiment, the logo area may be backlit by transmitting light through one or more openings in the first and second black masking layers in the logo area. | 10-22-2015 |
20150323831 | Flipped Panel Displays with Black Column Spacers - A liquid crystal display may have a thin-film transistor layer with an array of pixel electrode structures for applying electric fields to a liquid crystal layer. The liquid crystal display may also have a color filter layer with an array of color filter elements. The color filter elements may allow the display to display color images. The color filter layer may be interposed between the thin-film transistor layer and a backlight. The liquid crystal layer may be sandwiched between the thin-film transistor layer and the color filter layer. The color filter layer may have a transparent substrate on which the color filter elements are formed. Black masking structures may be formed on a transparent overcoat layer that covers the color filter elements. Black column spacers may be formed from the same layer of material that forms the black masking structures. | 11-12-2015 |
20150323843 | Electrostatic Discharge Protection Structures for Liquid Crystal Displays - A liquid crystal display having an outer layer such as a thin-film transistor layer and an inner layer such as a color filter layer may be mounted in a metal device housing. Transparent conductive coating material may be formed on display layers. The transparent conductive coating material may include a layer on the upper surface of the thin-film transistor layer, a layer on the lower surface of the color filter layer, and an edge coating that extends between the upper surface layer and lower surface layer. Electrostatic discharge protection structures for the display may include a conductive elastomeric gasket that couples the upper surface layer to an inner surface of the housing, a conductive tape that couples the lower surface layer to the inner surface, and a conductive material on the inner surface that contacts the edge coating. | 11-12-2015 |
20150338699 | Displays With Opaque Borders - A display may have an active area surrounded by an inactive border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. An upper polarizer may have a polarized central region that overlaps the active area of the display. The upper polarizer may also have an unpolarized portion in the inactive border area overlapping the border structures. The border structures may include colored material such as a white layer on the inner surface of the thin-film transistor layer. Binary information may be embedded into an array of programmable resonant circuits. The binary information may be a display identifier or other information associated with a display. The programmable resonant circuits may be tank circuits with adjustable capacitors, fuses, or other programmable components. | 11-26-2015 |
20150338951 | RC MATCHING IN A TOUCH SCREEN - A touch screen. In some examples, the touch screen can comprise a first element coupled to a first sense connection, and a second element coupled to a second sense connection. In some examples, the first and second sense connections can be configured such that a load presented by the first sense connection and the first element is substantially equal to a load presented by the second sense connection and the second element. In some examples, the first and second sense connections can comprise detour routing configured such that a resistance of the first sense connection is substantially equal to a resistance of the second sense connection. In some examples, the first and second sense connections can be coupled to dummy routing configured such that a first capacitance presented by the first sense connection is substantially equal to a second capacitance presented by the second sense connection. | 11-26-2015 |
20150362770 | Display with Low Reflectivity Alignment Structures - A display may have a thin-film transistor layer formed from a layer of thin-film, transistor circuitry on a substrate. The thin-film transistor layer may overlap a color filter layer. A portion of the thin-film transistor layer may extend past the color filter layer to for a ledge region. Components such as a flexible printed circuit and a display driver integrated circuit may be mounted to the thin-film transistor layer in the ledge region. The components may have alignment marks. The thin-film transistor layer may have a black masking layer that is patterned to form openings for display pixels. In a border area of the display that overlaps the ledge region, the thin-film transistor layer may have alignment mark viewing windows. Alignment marks formed from black masking material in the windows may be aligned with respective alignment marks on the components. | 12-17-2015 |
20160098144 | Display Having Vertical Gate Line Extensions and Touch Sensor - A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length. | 04-07-2016 |
20160098965 | Display Having Vertical Gate Line Extensions and Minimized Borders - A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length. | 04-07-2016 |
20160103349 | Display with Low Reflectivity Alignment Structures - A display may have a liquid crystal layer sandwiched between a thin-film transistor layer and a color filter layer. An upper polarizer may be placed on top of the thin-film transistor layer. A lower polarizer may be placed under the color filter layer. Components may be bonded to bond pads on the inner surface of the thin-film transistor layer using anisotropic conductive film. Bond quality may be assessed by probing probe pads that are coupled to the bond pads or by visually inspecting the bond pads through the thin-film transistor layer. Opaque masking material in the inactive area may be provided with openings to accommodate the bond pads. Additional opaque masking material may be placed on the underside of the upper polarizer and on the upper surface of the thin-film transistor layer to block the openings from view following visual inspection. | 04-14-2016 |
Patent application number | Description | Published |
20090121759 | FAST-SWITCHING LOW-NOISE CHARGE PUMP - In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump. | 05-14-2009 |
20090261917 | AUXILIARY VARACTOR FOR TEMPERATURE COMPENSATION - Techniques for compensating for the effects of temperature change on voltage controlled oscillator (VCO) frequency are disclosed. In an embodiment, an auxiliary varactor is coupled to an LC tank of the VCO. The auxiliary varactor has a capacitance controlled by a temperature-dependant control voltage to minimize the overall change in VCO frequency with temperature. Techniques for generating the control voltage using digital and analog means are further disclosed. | 10-22-2009 |
20090278620 | VCO CAPACITOR BANK TRIMMING AND CALIBRATION - Techniques are disclosed for trimming a capacitance associated with a capacitor bank for use in a voltage-controlled oscillator (VCO). In an embodiment, each capacitance is sub-divided into a plurality of constituent capacitances. The constituent capacitances may be selectively enabled or disabled to trim the step sizes of the capacitor bank. Further techniques are disclosed for calibrating the trimmable capacitance to minimize step size error for the capacitor bank. | 11-12-2009 |
20100225402 | VCO TUNING WITH TEMPERATURE COMPENSATION - Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described. | 09-09-2010 |
20100295622 | SYSTEMS AND METHODS FOR SELF TESTING A VOLTAGE CONTROLLED OSCILLATOR IN AN OPEN LOOP CONFIGURATION - Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured. | 11-25-2010 |
20110291716 | FAST-SWITCHING LOW-NOISE CHARGE PUMP - In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump. | 12-01-2011 |
20120187994 | SYSTEM FOR I-Q PHASE MISMATCH DETECTION AND CORRECTION - System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal. | 07-26-2012 |
20140253255 | VOLTAGE CONTROLLED OSCILLATOR BAND-SELECT FAST SEARCHING USING PREDICTIVE SEARCHING - A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold. | 09-11-2014 |
Patent application number | Description | Published |
20100160320 | C5aR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 06-24-2010 |
20100311753 | C5aR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 12-09-2010 |
20110275639 | C5aR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 11-10-2011 |
20130172347 | C5AR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 07-04-2013 |
20130317028 | C5aR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 11-28-2013 |
20150141425 | C5aR ANTAGONISTS - Compounds are provided that are modulators of the C5a receptor. The compounds are substituted piperidines and are useful in pharmaceutical compositions, methods for the treatment of diseases and disorders involving the pathologic activation of C5a receptors. | 05-21-2015 |
Patent application number | Description | Published |
20130093087 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130093088 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds. | 04-18-2013 |
20130095610 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130200533 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 08-08-2013 |
20130313012 | TSV FABRICATION USING A REMOVABLE HANDLING STRUCTURE - A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element. | 11-28-2013 |
20130328219 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer. | 12-12-2013 |
20140054763 | THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 02-27-2014 |
20150255424 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 09-10-2015 |
Patent application number | Description | Published |
20110011740 | CAPILLARY IMMUNOASSAY SYSTEMS AND METHODS - An automated assay system is described with stations for placement of materials to be used in an assay of materials inside capillaries and an automated gripper for manipulating capillaries. The system includes a separation/detection station where reactions inside the capillaries take place and photoemissions from the capillary reactions are detected. The photoemissions from the capillaries may be displayed as line graphs or in columns of a pseudo-gel image resembling the familiar Western gel blot. An automated control system has a user interface by which an operator can select a run protocol and define the locations of samples and reagents to be used in the protocol run. Following the setup the control system will cause the automated system to execute the protocol, then display the results in a selected display format. | 01-20-2011 |
20110195527 | METHODS AND DEVICES FOR ANALYTE DETECTION - Methods and apparatus are provided to resolve analytes within a fluid path using isoelectric focusing, gel electrophoresis, or other separation means. Materials within the fluid path that are compatible with these separation means are used to attach resolved analytes to the wall of the fluid path. Attachment results from a triggerable event such as photoactivation, thermal activation, or chemical activation. In accordance with a further aspect of the present invention, the material in the capillary may also be disrupted, by either the triggerable event or a subsequent event such as melting or photocleavage. Thus, an open lumen or porous structure may be created within the fluid path, allowing unbound analyte materials to be washed from the fluid path, and detection agents to be washed into the fluid path. The separation-compatible materials may be polymerizable monomers, gels, entangled polymers or other materials. | 08-11-2011 |
20120213667 | AUTOMATED MICRO-VOLUME ASSAY SYSTEM - An automated assay system is described with stations for placement of materials to be used in an assay of materials inside capillaries and an automated gripper for manipulating capillaries. The system includes a separation and immobilization station where reactions inside the capillaries take place and a detector station where photoemissions from the capillary reactions are detected. The photoemissions from the capillaries may be displayed as line graphs or in columns of a pseudo-gel image resembling the familiar Western gel blot. An automated control system has a user interface by which an operator can select a run protocol and define the locations of samples and reagents to be used in the protocol run. Following the setup the control system will cause the automated system to execute the protocol, then display the results in a selected display format. | 08-23-2012 |
20130167937 | AUTOMATED MICRO-VOLUME ASSAY SYSTEM - An automated assay system is described with stations for placement of materials to be used in an assay of materials inside capillaries and an automated gripper for manipulating capillaries. The system includes a separation and immobilization station where reactions inside the capillaries take place and a detector station where photoemissions from the capillary reactions are detected. The photoemissions from the capillaries may be displayed as line graphs or in columns of a pseudo-gel image resembling the familiar Western gel blot. An automated control system has a user interface by which an operator can select a run protocol and define the locations of samples and reagents to be used in the protocol run: Following the setup the control system will cause the automated system to execute the protocol, then display the results in a selected display format. | 07-04-2013 |
20150090591 | APPARATUS, SYSTEMS, AND METHODS FOR CAPILLARY ELECTROPHORESIS - An apparatus includes a body portion that defines a reservoir and a set of substantially flexible capillaries. The set of substantially flexible capillaries are fixedly coupled to the body portion and in fluid communication with the reservoir. A connector is configured to be coupled to the body portion to be in fluid communication with the reservoir and the set of substantially flexible capillaries. The connector is further configured to be coupled to a vacuum source. The apparatus is arranged such that at least a part of the body portion is electrically conductive. Methods for separating and detecting an analyte from a biological sample with the apparatus are also provided. For example, methods for separating and detecting one or more proteins from a cellular lysate or a purified protein are also provided. | 04-02-2015 |
Patent application number | Description | Published |
20080254552 | Methods and devices for analyte detection - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 10-16-2008 |
20090023225 | Methods and devices for analyte detection - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 01-22-2009 |
20090263290 | CAPILLARY STORAGE AND DISPENSING CONTAINER - A polymeric injection-molded container is described which holds capillaries for a biological material assay system in a vertical position. The container includes a two-piece base which is press-fit together. Ninety-six funnel-shaped holes in the top of the base receive the capillaries and support them circumferentially. Ninety-six apertures in the bottom of the base are tapered to guide the bottom ends of the capillaries to positions aligned with the holes in the top of the base. The inserted capillaries extend above the top surface of the base and are covered by a removable cover. The capillaries can be processed and placed in the container by the capillary manufacturer, shipped to a user in the container, and the container can be placed on the capillary holder station of an automated assay system and used by the automated system directly from the container. | 10-22-2009 |
20110132761 | METHODS AND DEVICES FOR ANALYTE DETECTION - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 06-09-2011 |
20140106372 | METHODS AND DEVICES FOR ANALYTE DETECTION - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 04-17-2014 |
Patent application number | Description | Published |
20110202105 | BIOELECTRIC BATTERY FOR IMPLANTABLE DEVICE APPLICATIONS - A bioelectric battery may be used to power implantable devices. The bioelectric battery may have an anode electrode and a cathode electrode separated by an insulating member comprising a tube having a first end and a second end, wherein said anode is inserted into said first end of said tube and said cathode surrounds said tube such that the tube provides a support for the cathode electrode. The bioelectric battery may also have a membrane surrounding the cathode to reduce tissue encapsulation. Alternatively, an anode electrode, a cathode electrode surrounding the cathode electrode, a permeable membrane surrounding the cathode electrode. An electrolyte is disposed within the permeable membrane and a mesh surrounds the permeable membrane. In an alternative embodiment, a pacemaker housing acts as a cathode electrode for a bioelectric battery and an anode electrode is attached to the housing with an insulative adhesive. | 08-18-2011 |
20140200644 | BIOELECTRIC BATTERY FOR IMPLANTABLE DEVICE APPLICATIONS - A bioelectric battery may be used to power implantable devices. The bioelectric battery may have an anode electrode and a cathode electrode separated by an insulating member comprising a tube having a first end and a second end, wherein said anode is inserted into said first end of said tube and said cathode surrounds said tube such that the tube provides a support for the cathode electrode. The bioelectric battery may also have a membrane surrounding the cathode to reduce tissue encapsulation. Alternatively, an anode electrode, a cathode electrode surrounding the cathode electrode, a permeable membrane surrounding the cathode electrode. An electrolyte is disposed within the permeable membrane and a mesh surrounds the permeable membrane. In an alternative embodiment, a pacemaker housing acts as a cathode electrode for a bioelectric battery and an anode electrode is attached to the housing with an insulative adhesive. | 07-17-2014 |
20140214110 | SYSTEMS AND METHODS TO MONITOR AND TREAT HEART FAILURE CONDITIONS - An implantable device monitors and treats heart failure, pulmonary edema, and hemodynamic conditions and in some cases applies therapy. In one implementation, the implantable device applies a high-frequency multi-phasic pulse waveform over multiple-vectors through tissue. The waveform has a duration less than the charging time constant of electrode-electrolyte interfaces in vivo to reduce intrusiveness while increasing sensitivity and specificity for trending parameters. The waveform can be multiplexed over multiple vectors and the results cross-correlated or subjected to probabilistic analysis or thresholding schemata to stage heart failure or pulmonary edema. In one implementation, a fractionation morphology of a sensed impedance waveform is used to trend intracardiac pressure to stage heart failure and to regulate cardiac resynchronization therapy. The waveform also provides unintrusive electrode integrity checks and 3-D impedancegrams. | 07-31-2014 |
20140276151 | SYSTEMS AND METHODS FOR OBTAINING SUBSTANTIALLY SIMULTANEOUS MULT-CHANNEL IMPEDANCE MEASUREMENTS AND RELATED APPLICATIONS - An implantable system includes terminals, a pulse generator, a sensing circuit, separate signal processing channels, and first, second and third multiplexers. The terminals are connected to electrodes via conductors of leads. Different subsets of the electrodes are used to define different electrical pulse delivery vectors, and different subsets of the electrodes are used to define different sensing vectors. The pulse generator produces electrical pulses, and the sensing circuit senses a signal indicative of an impedance associated with a selected sensing vector. The first multiplexer selectively connects outputs of the pulse generator to a selected one of the different electrical pulse delivery vectors at a time. The second multiplexer selectively connect inputs of the sensing circuit to a selected one of the different sensing vectors at a time. The third multiplexer selectively connects an output of the sensing circuit to one of the plurality of separate signal processing channels at a time. | 09-18-2014 |
20150282728 | SYSTEMS AND METHODS FOR OBTAINING SUBSTANTIALLY SIMULTANEOUS MULTI-CHANNEL IMPEDANCE MEASUREMENTS AND RELATED APPLICATIONS - An implantable system includes terminals, a pulse generator, a sensing circuit, separate signal processing channels, and first, second and third multiplexers. The terminals are connected to electrodes via conductors of leads. Different subsets of the electrodes are used to define different electrical pulse delivery vectors, and different subsets of the electrodes are used to define different sensing vectors. The pulse generator produces electrical pulses, and the sensing circuit senses a signal indicative of an impedance associated with a selected sensing vector. The first multiplexer selectively connects outputs of the pulse generator to a selected one of the different electrical pulse delivery vectors at a time. The second multiplexer selectively connect inputs of the sensing circuit to a selected one of the different sensing vectors at a time. The third multiplexer selectively connects an output of the sensing circuit to one of the plurality of separate signal processing channels at a time. | 10-08-2015 |
Patent application number | Description | Published |
20130329586 | IMPROVING RECEPTION BY A WIRELESS COMMUNICATION DEVICE - A method for improving reception by a wireless communication device is provided. The method can include a wireless communication device using a first RF chain to support a connection to a network via a first frequency band. The method can further include the wireless communication device tuning a second RF chain, which is not being actively used for carrier aggregation, to a second frequency band. The method can additionally include the wireless communication device measuring, via the second RF chain, a signal characteristic of the second frequency band. The method can also include the wireless communication device adjusting a configuration of the first RF chain based at least in part on the measured signal characteristic. | 12-12-2013 |
20130331077 | RF CHAIN MANAGEMENT IN A CARRIER AGGREGATION CAPABLE WIRELESS COMMUNICATION DEVICE - A method for managing radio frequency (RF) chains in a carrier aggregation capable wireless communication device is provided. The method can include a wireless communication device using a first RF chain associated with a first component carrier and a second RF chain associated with a second component carrier to support a connection to a network. The method can further include the wireless communication device formatting a deactivation message configured to trigger deactivation of the second component carrier. The method can additionally include the wireless communication device sending the deactivation message to the network to trigger deactivation of the second component carrier. The method can also include the wireless communication device discontinuing usage of the second RF chain to support the connection to the network via the second component carrier after sending the deactivation message. | 12-12-2013 |
20140143826 | POLICY-BASED TECHNIQUES FOR MANAGING ACCESS CONTROL - A policy-based framework is described. This policy-based framework may be used to specify the privileges for logical entities to perform operations associated with an access-control element (such as an electronic Subscriber Identity Module) located within a secure element in an electronic device. Note that different logical entities may have different privileges for different operations associated with the same or different access-control elements. Moreover, the policy-based framework may specify types of credentials that are used by the logical entities during authentication, so that different types of credentials may be used for different operations and/or by different logical entities. Furthermore, the policy-based framework may specify the security protocols and security levels that are used by the logical entities during authentication, so that different security protocols and security levels may be used for different operations and/or by different logical entities. | 05-22-2014 |
20150222635 | APPARATUS AND METHODS FOR CONTROLLED SWITCHING OF ELECTRONIC ACCESS CLIENTS WITHOUT REQUIRING NETWORK ACCESS - Methods and apparatuses for providing controlled switching of electronic access control clients without requiring network access are set forth herein. In one embodiment, a method for swapping of subscriptions and/or profiles for electronic Subscriber Identity Modules (eSIMs) without network supervision that prevents possibly malicious high frequency switching is disclosed. The disclosed embodiments offer reasonable management capabilities for network operators, without compromising the flexibility of eSIM operation. | 08-06-2015 |
20150289129 | TAMPER PREVENTION FOR ELECTRONIC SUBSCRIBER IDENTITY MODULE (eSIM) TYPE PARAMETERS - Disclosed herein are various techniques for preventing or at least partially securing parameters—e.g., Type parameters—of electronic Subscriber Identity Modules (eSIMs) stored within an embedded Universal Integrated Circuit Card (eUICC) from being inappropriately modified by mobile network operators (MNOs). One embodiment sets forth a technique that involves modifying file access properties of the Type parameters of eSIMs to make the Type parameters readable, but not updatable by the MNOs. Another embodiment sets forth a technique that involves implementing eSIM logical containers that separate the Type parameters from the eSIM data within the eUICC, such that the Type parameters are inaccessible to the MNOs. Yet another embodiment sets forth a technique that involves implementing an Operating System (OS)-based registry that is inaccessible to the MNOs and manages Type parameters for the eSIMs that are stored by the eUICC. | 10-08-2015 |
20150289137 | APPARATUS AND METHODS FOR CONTROLLED SWITCHING OF ELECTRONIC ACCESS CLIENTS WITHOUT REQUIRING NETWORK ACCESS - Methods and apparatuses for providing controlled switching of electronic access control clients (e.g., electronic Subscriber Identity Modules (eSIMs)) without requiring network access are set forth herein. In one embodiment, a method for swapping of subscriptions and/or profiles for without network supervision that prevents possibly malicious high frequency switching is disclosed. For example, a secure element included in a mobile device can be configured to issue, to a security module included in the mobile device, a request for the security module to carry out an authentication of a user of the mobile device. Upon determining, based on results received from the security module, that the authentication is successful, the secure element can generate one or more credits in accordance with the results, where each credit of the one or more credits can be used to carry out an eSIM management operation within the secure element. | 10-08-2015 |
20150341791 | ELECTRONIC SUBSCRIBER IDENTITY MODULE PROVISIONING - A method for preparing an eSIM for provisioning is provided. The method can include a provisioning server encrypting the eSIM with a symmetric key. The method can further include the provisioning server, after determining a target eUICC to which the eSIM is to be provisioned, encrypting the symmetric key with a key encryption key derived based at least in part on a private key associated with the provisioning server and a public key associated with the target eUICC. The method can additionally include the provisioning server formatting an eSIM package including the encrypted eSIM, the encrypted symmetric key, and a public key corresponding to the private key associated with the provisioning server. The method can also include the provisioning server sending the eSIM package to the target eUICC. | 11-26-2015 |
20150347786 | SECURE STORAGE OF AN ELECTRONIC SUBSCRIBER IDENTITY MODULE ON A WIRELESS COMMUNICATION DEVICE - A method for secure storage of an embedded Subscriber Identity Module (eSIM) on a wireless communication device including an embedded Universal Integrated Circuit Card (eUICC) and a memory external to the eUICC is provided. The method can include the eUICC determining that an eSIM package including an eSIM is to be stored on the memory. The method can also include the eUICC, in response to determining that the eSIM package is to be stored on the memory, maintaining a single-use session parameter associated with the eSIM package to enable installation of the eSIM on the eUICC if the eSIM package is later loaded onto the eUICC from the memory. | 12-03-2015 |
20150350879 | ELECTRONIC SUBSCRIBER IDENTITY MODULE APPLICATION IDENTIFIER HANDLING - Embodiments are described for identifying and accessing an electronic subscriber identity module (eSIM) and associated content of the eSIM in a multiple eSIM configuration. An embedded Universal Integrated Circuit Card (eUICC) can include multiple eSIMs, where each eSIM can include its own file structures and applications. Some embodiments include a processor of a mobile device transmitting a special command to the eUICC, including an identification that uniquely identifies an eSIM in the eUICC. After selecting the eSIM, the processor can access file structures and applications of the selected eSIM. The processor can then use existing commands to access content in the selected eSIM. The special command can direct the eUICC to activate or deactivate content associated with the selected eSIM. Other embodiments include an eUICC platform operating system interacting with eSIMs associated with logical channels to facilitate identification and access to file structures and applications of the eSIMs. | 12-03-2015 |
20160006729 | METHODS AND APPARATUS FOR ESTABLISHING A SECURE COMMUNICATION CHANNEL - A method for establishing a secure communication channel between an off-card entity and an embedded Universal Integrated Circuit Card (eUICC) is provided. The method involves establishing symmetric keys that are ephemeral in scope. Specifically, an off-card entity, and each eUICC in a set of eUICCs managed by the off-card entity, possess long-term Public Key Infrastructure (PKI) information. When a secure communication channel is to be established between the off-card entity and an eUICC, the eUICC and the off-card entity can authenticate one another in accordance with the respectively-possessed PKI information (e.g., verifying public keys). After authentication, the off-card entity and the eUICC establish a shared session-based symmetric key for implementing the secure communication channel. Specifically, the shared session-based symmetric key is generated according to whether perfect or half forward security is desired. Once the shared session-based symmetric key is established, the off-card entity and the eUICC can securely communicate information. | 01-07-2016 |
20160063260 | POLICY-BASED TECHNIQUES FOR MANAGING ACCESS CONTROL - A policy-based framework is described. This policy-based framework may be used to specify the privileges for logical entities to perform operations associated with an access-control element (such as an electronic Subscriber Identity Module) located within a secure element in an electronic device. Note that different logical entities may have different privileges for different operations associated with the same or different access-control elements. Moreover, the policy-based framework may specify types of credentials that are used by the logical entities during authentication, so that different types of credentials may be used for different operations and/or by different logical entities. Furthermore, the policy-based framework may specify the security protocols and security levels that are used by the logical entities during authentication, so that different security protocols and security levels may be used for different operations and/or by different logical entities. | 03-03-2016 |
Patent application number | Description | Published |
20100007238 | METHOD AND STRUCTURE FOR AN OUT-OF-PLANE COMPLIANT MICRO ACTUATOR - This present invention relates generally to manufacturing objects. More particularly, the invention relates to a method and structure for fabricating an out-of-plane compliant micro actuator. The compliant actuator has large actuation range in both vertical and horizontal planes without physical contact to the substrate. Due to fringe field actuation, the compliant actuator has no pull-in phenomenon and requires low voltage by a ‘zipping’ movement compared to conventional parallel plate electrostatic actuators. The method and device can be applied to micro actuators as well as other devices, for example, micro-electromechanical sensors, detectors, fluidic, and optical systems. | 01-14-2010 |
20100075481 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED IC-MEMS OSCILLATOR USING IC FOUNDRY-COMPATIBLE PROCESSES - The present invention relates to integrating an inertial mechanical device on top of an IC substrate monolithically using IC-foundry compatible processes. The IC substrate is completed first using standard IC processes. A thick silicon layer is added on top of the IC substrate. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. Compared with the incumbent bulk or surface micromachined MEMS inertial sensors, vertically monolithically integrated inertial sensors provided by embodiments of the present invention have one or more of the following advantages: smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost. | 03-25-2010 |
20100171153 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED PRESSURE SENSOR USING IC FOUNDRY-COMPATIBLE PROCESSES - A monolithically integrated MEMS pressure sensor and CMOS substrate using IC-Foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A diaphragm is then added on top of the CMOS. In one embodiment, the diaphragm is made of deposited thin films with stress relief corrugated structure. In another embodiment, the diaphragm is made of a single crystal silicon material that is layer transferred to the CMOS substrate. In an embodiment, the integrated pressure sensor is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated pressure sensor that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost. | 07-08-2010 |
20100187580 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED INFRARED SENSING DEVICE - Protection for infrared sensing device, and more particularly, to a monolithically integrated uncooled infrared sensing device using IC foundry compatible processes. The proposed infrared sensing device is fabricated on a completed IC substrate. In an embodiment, the infrared sensing device has a single crystal silicon plate with an absorbing layer supported a pair of springs. The absorbing layer absorbs infrared radiation and heats up the underlying silicon layer. As a result, an n well in the silicon layer changes its resistance related to its temperature coefficient of resistance (TCR). In another embodiment, the infrared sensing device has a top sensing plate supported by an underlying spring structures. The top sensing plate has sensing materials such as amorphous silicon, poly silicon, SiC, SiGe, Vanadium oxide, or YbaCuO. Finally, a micro lens array is placed on top of the sensing pixel array with a gap in between. In an embodiment, the micro lens array is fabricated on a silicon substrate and bonded to the sensing pixel array substrate. In another embodiment, the micro lens array is fabricated monolithically using amorphous silicon. The micro lens array layer encapsulates the pixel sensing array hermetically, preferably in a vacuum environment. | 07-29-2010 |
20100187652 | METHOD AND STRUCTURES OF MONOLITHICALLY INTEGRATED ESD SUPPRESSION DEVICE - This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs. | 07-29-2010 |
20110012166 | METHOD AND DEVICE FOR WAFER SCALE PACKAGING OF OPTICAL DEVICES USING A SCRIBE AND BREAK PROCESS - A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member. The one or more bonding pads and the antistiction region are exposed while the one or more deflection devices is maintained within the portion of the cavity region. | 01-20-2011 |
20110291934 | Touchscreen Operation Threshold Methods and Apparatus - A computer implemented method for performing a user-defined function in a computer system, performed by the computer system that is programmed to perform the method includes determining by a display a display position in response to a change and a rate change in state of a user-controlled user input device, determining by a physical sensor a magnitude of change in sensed physical in response to the rate of change in the state, determining whether the magnitude of change exceeds a threshold level, determining a function to perform in response to display position when magnitude of change in sensed physical properties exceeds the threshold level, initiating performance of the function in response to the function, and inhibiting performance of the function when the magnitude of change in sensed physical properties does not exceed the threshold level. | 12-01-2011 |
20110291981 | Analog Touchscreen Methods and Apparatus - A computer implemented method for determining an intensity of user input to a computer system, performed by the computer system that is programmed to perform the method includes determining by a display, an indication of a finger position a user in response to a change in finger position relative to the computer system, wherein change in fin position is also associated with a magnitude of change, determining by a physical sensor of the computer system, the magnitude of change in response to the change in finger position, determining by the computer system, a user selection of a function to perform in response to the indication of the finger position, determining by the computer system, an input parameter associated with the function in response to the magnitude of change, and initiating performance by the computer system, of the function in response to the input parameter. | 12-01-2011 |
20120139050 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED IC-MEMS OSCILLATOR USING IC FOUNDRY-COMPATIBLE PROCESSES - A three-dimensional integrated circuit device includes a first substrate having a first crystal orientation comprising at least one or more PMOS devices thereon and a first dielectric layer overlying the one or more PMOS devices. The three-dimensional integrated circuit device also includes a second substrate having a second crystal orientation comprising at least one or more NMOS devices thereon; and a second dielectric layer overlying the one or more NMOS devices. An interface region couples the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate. | 06-07-2012 |
20120248506 | METHOD AND STRUCTURE OF MONOLITHETICALLY INTEGRATED INERTIAL SENSOR USING IC FOUNDRY-COMPATIBLE PROCESSES - The present invention relates to integrating an inertial mechanical device on top of a CMOS substrate monolithically using IC-foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A thick silicon layer is added on top of the CMOS. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. | 10-04-2012 |
20120276677 | METHOD AND STRUCTURE OF WAFER LEVEL ENCAPSULATION OF INTEGRATED CIRCUITS WITH CAVITY - The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment. | 11-01-2012 |
20130065387 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED ESD SUPPERSSION DEVICE - A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs. | 03-14-2013 |
20130134599 | METHOD AND STRUCTURE OF INTEGRATED MICRO ELECTRO-MECHANICAL SYSTEMS AND ELECTRONIC DEVICES USING EDGE BOND PADS - A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures. | 05-30-2013 |
20130236988 | METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES - A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched. | 09-12-2013 |
20130285651 | THREE AXIS MAGNETIC SENSOR DEVICE AND METHOD - A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided. | 10-31-2013 |
20150270180 | METHOD AND STRUCTURE OF THREE DIMENSIONAL CMOS TRANSISTORS WITH HYBRID CRYSTAL ORIENTATIONS - A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate. | 09-24-2015 |
20150307347 | SYSTEM ON A CHIP USING INTEGRATED MEMS AND CMOS DEVICES - An integrated MEMS system in which CMOS and MEMS devices are provided to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured. | 10-29-2015 |
20160060102 | INTEGRATED CMOS AND MEMS DEVICES WITH AIR DIELETRICS - A monolithically integrated CMOS and MEMS device. The device includes a first semiconductor substrate having a first surface region and one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be provided overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate has a second surface region coupled to the CMOS surface region by bonding the second surface region to the bonding material. The second semiconductor substrate includes one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate. | 03-03-2016 |
Patent application number | Description | Published |
20090146264 | THIN FILM TRANSISTOR ON SODA LIME GLASS WITH BARRIER LAYER - The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the TFT. Substrates comprising a polyimide, because they are flexible, would also be attractive to utilize instead of non-alkali glass substrates, but the plastic substrates permit carbon to diffuse into the active layer. By depositing a silicon rich barrier layer over the soda lime glass substrate or substrate comprising a polyimide, both sodium and carbon diffusion may be reduced. Thus, a lower cost TFT may be produced with a soda lime glass substrate or a substrate comprising a polyimide as compared to a non-alkali glass substrate. | 06-11-2009 |
20090200553 | HIGH TEMPERATURE THIN FILM TRANSISTOR ON SODA LIME GLASS - The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the TFT. Substrates comprising a polyimide, because they are flexible, would also be attractive to utilize instead of non-alkali glass substrates, but the plastic substrates permit carbon to diffuse into the active layer. By depositing a silicon oxynitride adhesion layer over the soda lime glass substrate and a silicon rich barrier layer over the adhesion layer, diffusion may be reduced and deposition may occur at high temperatures. Thus, a lower cost TFT may be produced with a soda lime glass substrate or a substrate comprising a polyimide as compared to a non-alkali glass substrate. | 08-13-2009 |
20090261331 | LOW TEMPERATURE THIN FILM TRANSISTOR PROCESS, DEVICE PROPERTY, AND DEVICE STABILITY IMPROVEMENT - A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich silicon nitride layer. An active layer is formed, which may also be a bilayer, the first active layer deposited at a low rate and the second at a high rate. The thin film transistors described herein have superior mobility and stability under stress. | 10-22-2009 |
Patent application number | Description | Published |
20120230700 | Optical Module Design in an SFP Form Factor to Support Increased Rates of Data Transmission - A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads. | 09-13-2012 |
20130015557 | SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENTAANM Yang; ZhipingAACI CupertinoAAST CAAACO USAAGP Yang; Zhiping Cupertino CA USAANM Xue; JieAACI San RamonAAST CAAACO USAAGP Xue; Jie San Ramon CA USAANM Savic; JovicaAACI Downers GroveAAST ILAACO USAAGP Savic; Jovica Downers Grove IL USAANM Li; LiAACI San RamonAAST CAAACO USAAGP Li; Li San Ramon CA US - Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening. | 01-17-2013 |
20130122658 | MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE - A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device. | 05-16-2013 |
20140264904 | UNIFIED PCB DESIGN FOR SSD APPLICATIONS, VARIOUS DENSITY CONFIGURATIONS, AND DIRECT NAND ACCESS - Memory systems and methods for creating the same are disclosed. The memory systems can include pairs of IC packages mounted on either side of a system substrate. Contacts formed on the IC packages can be communicatively coupled with contacts of a paired IC package using vias that extend through the system substrate. The IC packages can further communicate with a controller mounted on one side of the system substrate using the vias as well as conductive traces formed in the system substrate. | 09-18-2014 |
20140264906 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 09-18-2014 |
20150325560 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 11-12-2015 |
20150342053 | Manufacturing a Semiconductor Package Including an Embedded Circuit Component within a Support Structure of the Package - An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device. | 11-26-2015 |
Patent application number | Description | Published |
20110204810 | APPARATUS, CIRCUIT AND METHOD FOR AUTOMATIC PHASE-SHIFTING PULSE WIDTH MODULATED SIGNAL GENERATION - Systems, circuits and methods for phase-shifting pulse width modulated signal generation are disclosed. In some embodiments, a phase-shifting pulse width modulation circuit is configured to output pulses based on an input pulse width modulated signal. The pulses are staggered relative to one another, and can be received by a light-emitting diode driver for driving a light-emitting diode string at one or more time periods. The phase-shifting pulse width modulation circuit can include a counter-based programmable delay subcircuit consisting of two counter-based programmable delay blocks. | 08-25-2011 |
20110267375 | LOAD-AWARE COMPENSATION IN LIGHT-EMITTING-DIODE BACKLIGHT ILLUMINATION SYSTEMS - System(s) and method(s) are provided for power management in an electronic display via compensation of a power source of a light-emitting-diode (LED) backlighting system. A compensation feedback loop includes a load-aware controller that receives the load condition from a dimming controller and supplies a control signal to the power source. An efficiency regulator functionally connected the backlight circuitry closes the compensation feedback loop and provides an input signal to the load-aware controller. The dimming controller implements phase-shifted pulse-modulation dimming, which based on duty cycle can establish a dimming equilibrium with two load conditions. The load aware controller includes a set of compensation blocks arranged in parallel, with a single compensation block connected to the input signal and that provides the control signal. A selector component in the load aware controller determines a compensation block to be connected to the compensation feedback loop based on the received load condition. | 11-03-2011 |
20130193859 | Apparatus, Circuit and Method for Automatic Phase-Shifting Pulse Width Modulated Signal Generation - Systems, circuits and methods for phase-shifting pulse width modulated signal generation are disclosed. In some embodiments, a phase-shifting pulse width modulation circuit is configured to output pulses based on an input pulse width modulated signal. The pulses are staggered relative to one another, and can be received by a light-emitting diode driver for driving a light-emitting diode string at one or more time periods. The phase-shifting pulse width modulation circuit can include a counter-based programmable delay subcircuit consisting of two counter-based programmable delay blocks. | 08-01-2013 |
20140139126 | LOAD-AWARE COMPENSATION IN LIGHT-EMITTING-DIODE BACKLIGHT ILLUMINATION SYSTEMS - System(s) and method(s) are provided for power management in an electronic display via compensation of a power source of a light-emitting-diode (LED) backlighting system. A compensation feedback loop includes a load-aware controller that receives the bad condition from a dimming controller and supplies a control signal to the power source. An efficiency regulator functionally connected the backlight circuitry closes the compensation, feedback loop and provides an input signal to the load-aware controller. The dimming controller implements phase-shifted pulse-modulation dimming, which based on duty cycle can establish a dimming equilibrium with two load conditions. The load aware controller includes a set of compensation blocks arranged in parallel, with a single compensation block connected to the input signal and that provides the control signal. A selector component in the load aware controller determines a compensation block to be connected to the compensation feedback loop based on the received load condition. | 05-22-2014 |
20140198886 | METHOD AND APPARATUS FOR FILTERING AND COMBINING MULTIPATH COMPONENTS OF A SIGNAL RECEIVED AT MULTIPLE ANTENNAS ACCORDING TO A WIRELESS COMMUNICATION PROTOCOL STANDARD FOR FILTERING A SIGNAL RECEIVED BY A SINGLE ANTENNA - A receiver communicating according to a wireless communication protocol standard for filtering a signal received at a single antenna. The receiver includes filter modules, receiver modules, and a summer. The filter modules receive from antennas multipath components of the signal as transmitted to the receiver. The signal includes bits of data. Each of the filter modules: receives corresponding ones of the multipath components of the signal as received at a respective one of the antennas; and according to the wireless communication protocol standard, filters the signal as received at the respective one of the antennas to generate a filtered signal. The receiver modules respectively receive the filtered signals. Each of the receiver modules combines the multipath components in the respective filtered signal to generate an output signal. Each of the output signals includes a respective version of the bits of data. The summer sums the output signals. | 07-17-2014 |
20150188603 | METHOD AND APPARATUS FOR FILTERING AND COMBINING MULTIPATH COMPONENTS OF A SIGNAL RECEIVED AT MULTIPLE ANTENNAS ACCORDING TO A WIRELESS COMMUNICATION PROTOCOL STANDARD DESIGNED FOR A RECEIVER HAVING ONLY A SINGLE RECEIVE ANTENNA - An interface including filter modules, receiver modules, and a summer. The filter modules are configured to receive from multiple antennas multipath components of a signal as transmitted to the interface. Each of the filter modules is configured to (i) receive corresponding ones of the multipath components of the signal as received at a respective one of the antennas, and (ii) according to a wireless communication protocol standard, filter the signal as received at the respective one of the antennas to generate a filtered signal. The wireless communication protocol standard is designed for a receiver having only a single antenna for receiving signals. The receiver modules are configured to respectively receive the filtered signals. Each of the receiver modules is configured to combine the multipath components in the respective filtered signal to generate an output signal. The summer is configured to sum the output signals. | 07-02-2015 |