Patent application number | Description | Published |
20120119606 | MOTOR STATOR AND ASSEMBLING METHOD THEREOF - A motor stator includes a stator unit and an auxiliary induction unit. The stator unit includes a circuit substrate, and a plurality of induction coils embedded within the circuit substrate. The auxiliary induction unit includes an insulating member, a magnetic conductor, and at least one coil winding assembly. The coil winding assembly includes a conductive rod and an auxiliary coil. The rod has an insert rod section extending through the magnetic conductor, the insulating member, and the circuit substrate, and a wound rod section permitting the auxiliary coil to be wound thereon, such that the auxiliary coil is disposed outwardly of the magnetic conductor. During assembly, the induction coil assembly is mounted to the magnetic conductor, and the insulating member is superposed on the circuit substrate. Subsequently, the rod is inserted through the insulating member and into the circuit substrate. | 05-17-2012 |
20120119607 | MOTOR STATOR - A motor stator includes an insulating frame having a plurality of projecting rods, an induction unit, and a plurality of conductive members. The induction unit includes an induction circuit board, a plurality of induction coils embedded within the induction circuit board, and a plurality of coil windings wound respectively on the projecting rods. The conductive members extend through the insulating frame and the induction circuit board for establishing an electrical connection between each of the induction coils and a corresponding one of the coil windings. The turn numbers of the coil windings are not limited by the area and thickness of the induction circuit board, and can be increased. Alternatively, the coil windings may be positioned to increase the magnetic pole slot number when energized. As such, a driving force of the motor stator can be increased. | 05-17-2012 |
20120119608 | MOTOR STATOR - A motor stator includes a stator unit and at least one auxiliary unit. The stator unit includes a circuit substrate, and a plurality of spaced-apart induction coils embedded within the circuit substrate. The auxiliary unit includes an auxiliary coil attached to and disposed outwardly of the circuit substrate. | 05-17-2012 |
Patent application number | Description | Published |
20100181500 | METHOD AND SYSTEM FOR LOW TEMPERATURE ION IMPLANTATION - A method comprises pre-cooling a first semiconductor wafer outside of a process chamber, from a temperature at or above 15° C. to a temperature below 5° C. The pre-cooled first wafer is placed inside the process chamber after performing the pre-cooling step. A low-temperature ion implantation is performed on the first wafer after placing the first wafer. | 07-22-2010 |
20100240224 | MULTI-ZONE SEMICONDUCTOR FURNACE - A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers. | 09-23-2010 |
20100248496 | ROTATABLE AND TUNABLE HEATERS FOR SEMICONDUCTOR FURNACE - A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers. | 09-30-2010 |
20120079289 | SECURE ERASE SYSTEM FOR A SOLID STATE NON-VOLATILE MEMORY DEVICE - A secure erase system for a solid state memory device is disclosed. A memory area provides a data block for storing data and a key block for storing at least one key. A translation unit maps a logical address to a physical address associated with the memory area. An encryption unit encrypts plaintext data to be written to the memory area with the associated key and decrypts the encrypted data to be read by a host with the associated key. The key associated with a logical erase group to be secure erased is deleted after receiving a command requesting to erase the data associated with the logical erase group. | 03-29-2012 |
20120098006 | LIGHT EMITTING DIODE PACKAGE WITH PHOTORESIST REFLECTOR AND METHOD OF MANUFACTURING - Optical emitters are fabricated by forming and shaping photoresist reflectors on a package wafer using lithography processes, and bonding Light-Emitting Diode (LED) dies to the package wafer. | 04-26-2012 |
20120104435 | REFRACTIVE INDEX TUNING OF WAFER LEVEL PACKAGE LEDS - Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens. | 05-03-2012 |
20120104450 | LIGHT EMITTING DIODE OPTICAL EMITTER WITH TRANSPARENT ELECTRICAL CONNECTORS - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 05-03-2012 |
20120244652 | METHODS OF FABRICATING LIGHT EMITTING DIODE DEVICES - An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor. | 09-27-2012 |
20120264296 | METHODS OF FORMING THROUGH SILICON VIA OPENINGS - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 10-18-2012 |
20120292629 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process. | 11-22-2012 |
20120305956 | LED PHOSPHOR PATTERNING - The present disclosure provides a method of patterning a phosphor layer on a light emitting diode (LED) emitter. The method includes providing at least one LED emitter disposed on a substrate; forming a polymer layer over the at least one LED emitter; providing a mask over the polymer layer and the at least one LED emitter; etching the polymer layer through the mask to expose the at least one LED emitter within a cavity having polymer layer walls; and coating the at least one LED emitter with phosphor. | 12-06-2012 |
20130089937 | METHOD AND APPARATUS FOR ACCURATE DIE-TO-WAFER BONDING - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 04-11-2013 |
20130171746 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-04-2013 |
20130260484 | OPTIMIZING LIGHT EXTRACTION EFFICIENCY FOR AN LED WAFER - The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters. | 10-03-2013 |
20130330938 | ROTATABLE AND TUNABLE HEATERS FOR SEMICONDUCTOR FURNACE - A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers. | 12-12-2013 |
20140065741 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 03-06-2014 |
20140093990 | Light Emitting Diode Optical Emitter with Transparent Electrical Connectors - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 04-03-2014 |
20140235053 | Methods of Forming Through Silicon Via Openings - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 08-21-2014 |
20140239323 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath. | 08-28-2014 |
20140252380 | Shadow Mask Assembly - A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly. | 09-11-2014 |
20150083998 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A light-emitting diode (LED) element includes a substrate and a GaN layer formed on the substrate. The GaN layer includes a boundary layer including a surface of the GaN opposing the substrate. The surface has a micro-roughening texture and a macro-roughening texture. The boundary layer includes at least one of As, Si, P, Ge, C, B, F, N, Sb, and Xe ions. | 03-26-2015 |
20150211122 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-30-2015 |