Dray
Alexandre Dray, Crolles FR
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20120275075 | Electrostatic Discharge Protection Device - Semiconducting device for protecting at least one node of an integrated circuit against electrostatic discharges, comprising a doublet of floating gate thyristors connected in parallel and head-to-foot, the two thyristors having respectively two distinct gates and a common gate formed by a common semiconducting layer, the anode of a first thyristor of the doublet and the cathode of the second thyristor of the doublet forming a first terminal of the doublet designed to be connected to a cold point and the cathode of the first thyristor of the doublet and the anode of the second thyristor of the doublet forming a second terminal of the doublet designed to be connected to the said node to be protected. | 11-01-2012 |
Alexandre Dray, Moretel De Mailles FR
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20100027174 | CIRCUIT FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES IN CMOS TECHNOLOGY - The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch. | 02-04-2010 |
Cedric Dray, Toulouse FR
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20150290286 | PHARMACEUTICAL COMPOSITION FOR USE IN THE TREATMENT OF DYSFUNCTION ASSOCIATED WITH AGING - The present invention relates to an APJ receptor agonist or an apelinomimetic for use in the treatment or the prevention of a dysfunction associated with aging. | 10-15-2015 |
Cyrille Dray, Portland, OR US
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20140153313 | System and Methods Using a Multiplexed Reference for Sense Amplifiers - A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase. | 06-05-2014 |
Cyrille Dray, Antibes FR
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20080290899 | Integrated circuit and method of detecting a signal edge transition - The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level. | 11-27-2008 |
20090027987 | Memory Device and Testing - An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed. | 01-29-2009 |
20110128767 | Memory With Intervening Transistor - Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition. | 06-02-2011 |
20120099359 | Nonvolatile Memory Architecture - Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array. | 04-26-2012 |
20120218830 | METHOD AND SYSTEM FOR READING FROM MEMORY CELLS IN A MEMORY DEVICE - A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier. | 08-30-2012 |
Cyrille Dray, Grenoble FR
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20080218211 | High-speed buffer circuit, system and method - A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation. | 09-11-2008 |
20100265758 | Method for implementing an SRAM memory information storage device - A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column. | 10-21-2010 |
Cyrille Dray, Hillsboro, OR US
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20140340977 | LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL - Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node. | 11-20-2014 |
20150117095 | LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY - Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells. | 04-30-2015 |
20150179247 | APPARATUS FOR DUAL PURPOSE CHARGE PUMP - Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed. | 06-25-2015 |
Donald D. Dray, Rockford, IL US
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20120186149 | Garden Support System and Method - A garden support system according to one embodiment includes a plurality of support poles having a generally elongated pole body. At least one of the support poles has a first end that includes a tapered portion for insertion into a support medium. The system includes a plurality of alignment members for joining the support poles in a grid arrangement for supporting at least one plant. The alignment members each have a pair of channels each for receiving a corresponding support pole therein. When the alignment members and support poles are joined, the alignment members hold the support poles in place by a friction fit between the respective pole bodies and channels and permit adjustment of the grid arrangement by sliding an alignment member along a corresponding pole body. | 07-26-2012 |
Edward Dray, Uniontown, OH US
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20150211640 | Fill Valve Apparatus - A first valve member has an axis and a first seat surface with a tapered contour facing axially downstream. A second valve member has a second seat surface with a tapered contour facing axially upstream. The second valve member has a closed position in which the second seat surface abuts the first seat surface, and has an open position in which the second seat surface is spaced axially downstream from the first seat surface. The second valve member further has a terminal end portion configured as a nose cone. The nose cone may be located entirely downstream of the second seat surface, and may have a cavity with a drain opening. | 07-30-2015 |
Edward A. Dray, Uniontown, OH US
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20150089988 | ROLL CHANGE APPARATUS - A rolling machine has pairs of rolls in a horizontal line of roll pair locations, with each pair including upper and lower rolls opposed across a vertical gap. A sliding frame is mounted on the rolling machine for movement alongside the rolling machine in a direction parallel to the line of roll pair locations. A lifting frame is mounted on the sliding frame for movement vertically relative to the sliding frame beside each of the roll pair locations. Other parts include a roll cassette and a load tray. The load tray is configured to carry the roll cassette, and is mounted on the lifting frame for movement relative to the lifting frame transversely into the vertical gap between the rolls at each roll pair location. | 04-02-2015 |
Karl Dray, San Francisco, CA US
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20150160969 | AUTOMATED INVALIDATION OF JOB OUTPUT DATA IN A JOB-PROCESSING SYSTEM - A computing system can provide user interfaces and back-end operations to facilitate review and invalidation of executed jobs. The system can provide an interface that allows the operator to review quality-control information about a completed job. Once the operator identifies a job as invalid, the operator can be presented with further options, such as whether to invalidate only the reviewed job or the job and all its descendants. The operator can also review antecedent jobs to an invalid job (e.g., in order to trace the root of the problem) and can selectively invalidate antecedent jobs. | 06-11-2015 |
20150160974 | JOB-PROCESSING SYSTEMS AND METHODS WITH INFERRED DEPENDENCIES BETWEEN JOBS - An analytics system that executes processing jobs infers dependencies between jobs to be executed based on identification of dependencies between a “sink” job and a source data object on which the sink job depends. Given a job definition for the sink job that identifies a source data object, the system can identify a “source” job that produces the source data object and can infer a dependency of the sink job on the source job. The system can schedule executions of the source and sink jobs such that the source job completes (or completes generation of the source data object) before the sink job is launched. | 06-11-2015 |
Richard C. Dray, Rochester, NY US
Patent application number | Description | Published |
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20100178086 | APPARATUS AND METHOD FOR DETACHING MEDIA FROM A FUSER IN A PRINTER - An apparatus ( | 07-15-2010 |