Patent application number | Description | Published |
20130119476 | Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 05-16-2013 |
20130126978 | CIRCUITS WITH LINEAR FINFET STRUCTURES - A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. | 05-23-2013 |
20130146988 | Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 06-13-2013 |
20130193524 | Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-01-2013 |
20130200463 | Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-08-2013 |
20130200464 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-08-2013 |
20130200465 | Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes two conductive contacting structures at a location not over an inner non-diffusion region. | 08-08-2013 |
20130200469 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks With Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-08-2013 |
20130207196 | Cross-Coupled Transistor Circuit Defined on Four Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-15-2013 |
20130207197 | Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts - A first conductive gate level feature forms a gate electrode of a first transistor of a first transistor type. A second conductive gate level feature forms a gate electrode of a first transistor of a second transistor type. A third conductive gate level feature forms a gate electrode of a second transistor of the first transistor type. A fourth conductive gate level feature forms a gate electrode of a second transistor of the second transistor type. A first contact connects to the first conductive gate level feature over an inner non-diffusion region. The first and fourth conductive gate level features are electrically connected through the first contact. A second contact connects to the third conductive gate level feature over the inner non-diffusion region and is offset from the first contact. The third and second conductive gate level features are electrically connected through the second contact. | 08-15-2013 |
20130207198 | Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-15-2013 |
20130207199 | Finfet Transistor Circuit - A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned. | 08-15-2013 |
20130254732 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 09-26-2013 |
20140197543 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 07-17-2014 |
20140210015 | Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure. | 07-31-2014 |
20140239408 | SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a second transistor of the first transistor type. A fourth LCS forms a GE of a second transistor of the second transistor type. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. The electrical connection areas of the first and third LCS's are offset from each other. The GE of the first transistor of the first transistor type is electrically connected to the GE of the second transistor of the second transistor type. The GE of the second transistor of the first transistor type is electrically connected to the GE of the first transistor of the second transistor type. | 08-28-2014 |
20140291730 | Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration. | 10-02-2014 |
20140367799 | Semiconductor Chip Including Digital Logic Circuit Including At Least Nine Linear-Shaped Conductive Structures Collectively Forming Gate Electrodes of At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods - At least nine linear-shaped conductive structures (LCS's) are positioned in accordance with a first pitch. Five of the at least nine LCS's collectively form three transistors of a first transistor type and three transistors of a second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Two transistors of the first transistor type and two transistors of the second transistor type are cross-coupled transistors. Each of four LCS's corresponding to the cross-coupled transistors has a respective electrical connection area located within the inner region. The two LCS's corresponding to the two transistors of the first transistor type of the cross-coupled transistors have electrical connections areas that are not aligned with each other. The four LCS's corresponding to the cross-coupled transistors include at least two different inner extension distances beyond their respective electrical connection areas. | 12-18-2014 |
20150187769 | Semiconductor Chip Including Digital Logic Circuit Including At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and one or more conductive interconnect structures. | 07-02-2015 |
20160079159 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 03-17-2016 |
20160079276 | Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same - A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. | 03-17-2016 |
Patent application number | Description | Published |
20120002557 | Method for Self Organizing Network Operation - The present invention relates to wireless cellular telecommunication networks and, in particular, to control and management of self organizing wireless cellular telecommunication network. A method for network planning and frequency optimization in LTE networks by determining the optimal base station configuration parameters, comprises a base station initialization, an initial base station configuration, an iterative measurement procedure, an optimization process, a verification of operation, and a periodical maintenance procedure. | 01-05-2012 |
20120063315 | Method for Congestion Avoidance in 4G Networks - This invention aims to avoid and resolve congestions in wireless 4G networks. The method is based on a central self-organizing network (SON) server, which dynamically changes neighbor lists on congested base station and on all base stations in vicinity. The procedure is triggered by measuring relative committed traffic rate and air interface utilization of the base station. When base station enters into congested state, it notifies the SON server. The SON server creates new neighbor lists for all base stations in the vicinity and removes the congested base station from these lists. With new neighbor lists propagated to mobile stations, the latter won't scan and initiate handovers to the congested base station. The SON server additionally creates a new dense neighbor list and changes handover triggers settings of the congested base station. The mobile stations consequently find other handover opportunities and connect to different base stations. As the air interface resources are released, the base station leaves the congested state. | 03-15-2012 |
20120064832 | Method for 4G Node Frequency Selection - A method for 4G node frequency selection describes a mechanism for automatically selecting the frequency of a newly installed base station, thereby optimizing the throughput per area unit of the newly installed base station in its predefined vicinity area. The method is based on an iterative calculation approach which combines real-world network and base station measurements information with the nominal specifications of the newly installed base station (antenna diagram, output power) and the location and direction thereof. | 03-15-2012 |
20120083279 | Method for Cognitive 4G Neighborhood Selection - A method for cognitive neighbor selection in 4G networks describes a mechanism for automatic self-learning selection of neighboring base stations for the purpose of providing seamless handoffs in a dense deployment of pico and macro base stations. When a 4G network is modified by adding new base stations, the optimum handoff thresholds and advertised base station neighbors are automatically recalculated in a manner that reduces the number of unnecessary handoffs in a dense network with large number of pico and macro base stations. | 04-05-2012 |
Patent application number | Description | Published |
20140342456 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 11-20-2014 |
20140342457 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 11-20-2014 |
20140342458 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 11-20-2014 |
20140356956 | RNA-Guided Transcriptional Regulation - Methods of modulating expression of a target nucleic acid in a cell are provided including introducing into the cell a first foreign nucleic acid encoding one or more RNAs complementary to DNA, wherein the DNA includes the target nucleic acid, introducing into the cell a second foreign nucleic acid encoding a nuclease-null Cas9 protein that binds to the DNA and is guided by the one or more RNAs, introducing into the cell a third foreign nucleic acid encoding a transcriptional regulator protein or domain, wherein the one or more RNAs, the nuclease-null Cas9 protein, and the transcriptional regulator protein or domain are expressed, wherein the one or more RNAs, the nuclease-null Cas9 protein and the transcriptional regulator protein or domain co-localize to the DNA and wherein the transcriptional regulator protein or domain regulates expression of the target nucleic acid. | 12-04-2014 |
20140356958 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 12-04-2014 |
20140356959 | RNA-Guided Transcriptional Regulation - Methods of modulating expression of a target nucleic acid in a cell are provided including introducing into the cell a first foreign nucleic acid encoding one or more RNAs complementary to DNA, wherein the DNA includes the target nucleic acid, introducing into the cell a second foreign nucleic acid encoding a nuclease-null Cas9 protein that binds to the DNA and is guided by the one or more RNAs, introducing into the cell a third foreign nucleic acid encoding a transcriptional regulator protein or domain, wherein the one or more RNAs, the nuclease-null Cas9 protein, and the transcriptional regulator protein or domain are expressed, wherein the one or more RNAs, the nuclease-null Cas9 protein and the transcriptional regulator protein or domain co-localize to the DNA and wherein the transcriptional regulator protein or domain regulates expression of the target nucleic acid. | 12-04-2014 |
20150232833 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 08-20-2015 |
20160002670 | RNA-Guided Human Genome Engineering - A method of altering a eukaryotic cell is provided including transfecting the eukaryotic cell with a nucleic acid encoding RNA complementary to genomic DNA of the eukaryotic cell, transfecting the eukaryotic cell with a nucleic acid encoding an enzyme that interacts with the RNA and cleaves the genomic DNA in a site specific manner, wherein the cell expresses the RNA and the enzyme, the RNA binds to complementary genomic DNA and the enzyme cleaves the genomic DNA in a site specific manner. | 01-07-2016 |
Patent application number | Description | Published |
20090158895 | Process for the Production of Titanium Products - The invention provides a method for the Industrial purification of a titanium feed stream of purity P1, by the formation of a titanium-double-salt precipitate of purity P2 and a titanium solution with purity P3, wherein P2>P1>P3, the method comprising the steps of: i. forming, from the feed, a medium comprising water, titanium ion, a cation selected from the group consisting of ammonium, cations of alkali metals, protons and a combination thereof, and an anion selected from the group consisting of OH, SO4, HSO4, halides and a combination thereof, which formed medium is further characterized by the presence of (a) a double-salt precipitate comprising titanium ion, at least one of the cations and at least one of the anions; and (b) a titanium solution; and wherein the concentration of the anion in the titanium solution is higher than 15% and the ratio between the concentrations of the cation and the anion in the titanium solution is higher than 0.2 and lower than 1.6; and ii. separating at least a portion of the precipitate from the solution. | 06-25-2009 |
20120264873 | SUGAR MIXTURES AND METHODS FOR PRODUCTION AND USE THEREOF - A sugar mixture comprising: monosaccharides; oligosaccharides in a ratio ≧0.06 to total saccharides; disaccharides in a ratio to total saccharides ≧0.05; pentose in a ratio to total saccharides ≧0.05; at least one alpha-bonded di-glucose; and at least one beta-bonded di-glucose. Also disclosed are methods to make and/or use such mixtures. | 10-18-2012 |
20120301389 | METHOD FOR THE SEPARATION OF A NON-VOLATILE STRONG ACID FROM A SALT THEREOF AND COMPOSITIONS PRODUCED THEREBY - The present invention provides an organic phase composition comprising
| 11-29-2012 |
20130028832 | METHODS FOR THE SEPARATION OF HCL FROM A CARBOHYDRATE AND COMPOSITIONS PRODUCED THEREBY - The present invention provides an organic phase composition comprising:
| 01-31-2013 |
20130028833 | METHOD FOR PREPARING A HYDROLYZATE - The present invention provides an organic phase composition comprising
| 01-31-2013 |
20140190470 | METHODS AND SYSTEMS FOR PROCESSING A SUCROSE CROP AND SUGAR MIXTURES - A method comprising: (a) providing a partially processed sucrose crop product containing at least 2% optionally at least 5% of the sucrose content of said crop at harvest on a dry solids basis, cellulose and lignin; (b) hydrolyzing said partially processed crop product with HCl to produce an acid hydrolyzate stream and a lignin stream; and (c) de-acidifying said hydrolyzate stream to produce a de-acidified sugar solution and an HCl recovery stream. Additional, methods, systems and sugar mixtures are also disclosed. | 07-10-2014 |
Patent application number | Description | Published |
20120270842 | Inhibitors of Diacylglycerol O-Acyltransferase 1 (DGAT-1) and Uses Thereof - The invention pertains to use of DGAT-1 inhibitors to treat and/or prevent overweight, obesity and various diseases and disorders associated therewith. Other conditions also can be ameliorated or avoided, such as high postprandial triglycerides or diet-related hypertriglyceridemia, cardiovascular risk associated with excessive triglycerides, and insulin resistance/glucose intolerance in overweight patients, those with diabetes or other glucose metabolic disorders such as Syndrome X and/or polycystic ovary disease. Compounds and compositions suitable for use in the disclosed methods are also provided. | 10-25-2012 |
20130165423 | SUBSTITUTED BENZIMIDAZOLES AND BENZOPYRAZOLES AS CCR(4) ANTAGONISTS - Benzimidazole, benzopyrazole and benzotriazole compounds are provided which bind to CCR(4) and are useful for the treatment of diseases such as allergic diseases, autoimmune diseases, graft rejection and cancer. | 06-27-2013 |
20130172315 | SUBSTITUTED ANILINES AS CCR(4) ANTAGONISTS - Aniline compounds are provided which bind to CCR(4) and are useful for the treatment of diseases such as allergic diseases, autoimmune diseases, graft rejection and cancer. | 07-04-2013 |
20140121195 | SUBSTITUTED BENZIMIDAZOLES AND BENZOPYRAZOLES AS CCR(4) ANTAGONISTS - Benzimidazole, benzopyrazole and benzotriazole compounds are provided which bind to CCR(4) and are useful for the treatment of diseases such as allergic diseases, autoimmune diseases, graft rejection and cancer. | 05-01-2014 |
20150141397 | SUBSTITUTED ANILINES AS CCR(4) ANTAGONISTS - Aniline compounds are provided which bind to CCR(4) and are useful for the treatment of diseases such as allergic diseases, autoimmune diseases, graft rejection and cancer. | 05-21-2015 |
20150175547 | CCR6 COMPOUNDS - Compounds of formula (I) are provided which are useful in the treatment of diseases or conditions modulated at least in part by CCR6: | 06-25-2015 |