Patent application number | Description | Published |
20090167397 | Delay device for adjusting phase SMIA standard - A delay device for adjusting phase under a SMIA (Standard Mobile Imaging Architecture) standard is provided. More particularly, the delay device is used to adjust a phase of a clock signal, which carries data, under the SMIA standard. The delay device includes plural delay cells, which are disposed on a circuit board by means of APR (Automated Placement and Routing) method, and one or more delay multiplexers (MUX) connected with the delay cells. Through selective pins controlling the route selection in the delay multiplexer, the delay device can produce plural delay times to adjust the phase relationship between data and clock, as supposed to using PLL. | 07-02-2009 |
20090167572 | Serial/Parallel data conversion apparatus and method thereof - A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency divider and a delay controller. Moreover, the first data register converts the serial data into the parallel data according to a first working clock signal. The frequency divider performs a frequency division for the first working clock signal for producing a second working clock signal. The second data register acquires the parallel data from the first register according to the second working clock signal. The delay controller delays the second working clock signal to produce a third working clock signal. Finally, the third data register obtains the parallel data from the second register according to the third working clock signal. | 07-02-2009 |
20120106861 | IMAGE COMPRESSION METHOD - A compressing method is applicable to compress of an image at a fixed compression ratio, in which the image has a raw data. The compression method includes the steps of receiving the raw data with a predetermined length as a compression unit; compressing the compression unit into a compressed bit stream, wherein a total length of the compressed bit stream being not larger than a target bit stream length; when the total length of the compressed bit stream is smaller than the target bit stream length, appending a dummy code to the compressed bit stream, so that a bit stream length of the compressed bit stream with the dummy code is equal to the target bit stream length; and repeating steps until the raw data is compressed into an image bit stream. | 05-03-2012 |
Patent application number | Description | Published |
20080218092 | Christmas light string with socket for connecting to another christmas light string - A Christmas light string is disclosed and includes a plug a power socket, a first cord electrically interconnecting the plug and the power socket, a second cord extending from the plug and being electrically connected thereto, an adapter proximate the plug and mounted in the second cord, and a plurality of lamps electrically connected in series or parallel and mounted along the second cord and distal the plug. The plug of another Christmas light string is adapted to electrically connect to the power socket by insertion. Hence, a number of Christmas light strings can be assembled together to form a lighting unit having an increased length. | 09-11-2008 |
20090322236 | Christmas light string with LED bulb loop and incandescent light bulb loop - A Christmas light string includes a plug; a first negative wire together with a first positive wire and the plug forming a circuit; incandescent light bulbs connected together along the first positive and negative wires to form a first loop; a rectifier having a positive input connected to the first incandescent light bulb via a second positive wire and a negative input connected to the last incandescent light bulb via a second negative wire; an end enlargement connected to the positive input of the rectifier via the second positive wire and the negative input of the rectifier via the second negative wire; and LED bulbs forming a second loop between the positive output and the negative output of the rectifier. An optimum illumination is rendered by mixing cold light with warm light. Moreover, mating sockets are adapted to receive the incandescent light bulbs only. | 12-31-2009 |
20100079076 | LED LIGHT STRING WITHOUT ADDITIONAL RESISTORS - An electrical circuit for use as a string of lights in one embodiment includes a rectifier for converting AC into DC; and a plurality of lamps connected in series, each lamp having an LED, and wherein at least one of the lamps each has a Zener diode connected in series with the LED, a positive terminal of the lamp proximate the rectifier is connected to a positive terminal of an output of the rectifier, and a negative terminal of the lamp distal the rectifier is connected to a negative terminal of the output of the rectifier. In another embodiment, the Zener diode is replaced with a resistor. Hence, no resistors are provided externally of the lamp. | 04-01-2010 |
20100102735 | LED LIGHT STRING WITH ZENER DIODES OR RESISTORS AS SHUNTS - A light string in one embodiment includes a plurality of lamps connected in series, each lamp having a shunt Zener diode; and a rectifier. An anode of the Zener diode of each lamp is connected to a cathode of the LED thereof, the cathode of the Zener diode of each lamp is connected to the anode of the LED thereof, the cathode of the Zener diode of the lamp proximate the rectifier is connected to a positive terminal of an output of the rectifier, and the anode of the Zener diode of the lamp distal the rectifier is connected to a negative terminal of the output of the rectifier. The Zener diodes are replaced by resistors in another embodiment. Hence, a burned out LED of one lamp will not adversely affect a normal operation of the light string. | 04-29-2010 |
20100109553 | LED BULB WITH ZENER DIODE, ZENER DIODE ASSEMBLY OR RESISTOR CONNECTED IN SERIES - An LED bulb in one embodiment includes two depending arms; a Zener diode secured to one end of one arm; an LED secured to one end of the other arm; a conductor electrically interconnecting the Zener diode and the LED; and an enclosure formed of epoxy resin with the Zener diode, the LED, the conductor, and one ends of the arms being concealed therein, wherein either a cathode of the LED is connected in series with a cathode of the Zener diode or an anode of the LED is connected in series with an anode of the Zener diode. The LED is adapted to emit red, green, or blue light. | 05-06-2010 |
20100148694 | LED light string with capacitor based rectifier filter for increasing output voltage - A string of LED light is provided. The string of LED light has a full-wave rectifier with a capacitor based filter for increasing output voltage to the range of 2.6 to 2.84 times as compared with the output voltage of a typical full-wave rectifier without filter so that an increased number of lamps each having an LED and a Zener diode in parallel therewith can be attached to the string of LED light. | 06-17-2010 |
20100207533 | Light string with alternate LED lamps and incandescent lamps - In one embodiment an electrical circuit for use as a string of lights includes a load comprising a plurality of lamps connected in series, the lamps comprising a first group of lamps including an LED and a first Zener diode in parallel therewith, and a second group of lamps including an incandescent light bulb and a second Zener diode in parallel therewith; and a rectifier for converting a source of AC into DC which is supplied to the load. The first group of lamps are alternate with the second group of lamps. | 08-19-2010 |
Patent application number | Description | Published |
20110079906 | PRE-PACKAGED STRUCTURE - A pre-packaged structure includes a substrate with a substrate circuit, a die having a core circuit and disposed on the substrate, a passivation selectively covering the core circuit, a buffer metal layer electrically connected to the core circuit and completely covering the passivation and a copper wire bond electrically connected to the buffer metal layer and the substrate circuit. | 04-07-2011 |
20110316601 | Method and Device for Delaying Activation Timing of Output Device - A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a first mirror current, delaying an enable signal of the circuit system according to the first mirror current to generate a charging activation signal, providing a charging current according to the charging activation signal, and determining the activation moment of the output device according to the activation current. | 12-29-2011 |
20110317317 | Method and Device for Delaying Activation Timing of Output Device - A delay method for determining an activation time of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a division current, drawing the division current from a charging current to determine an activation current of the output device, and determining the activation time point of the output device according to the activation current. | 12-29-2011 |
20120139058 | POWER MOS DEVICE - A power MOS device having a gate with crosshatched lattice pattern on a substrate and at lease a source or a drain isolated by the gate, characterized in that the source has only one diffusion region of a pre-selected conductivity type. According to one embodiment, the source has a source diffusion of first conductivity type and the drain has a drain diffusion of first conductivity type. The source diffusion is replaced with substrate contact diffusion at some source sites across the transistor array. | 06-07-2012 |
20120176178 | SWITCH CIRCUIT CAPABLE OF PREVENTING VOLTAGE SPIKE, AND CONTROL METHOD AND LAYOUT STRUCTURE THEREOF - A switch circuit capable of preventing voltage spike, includes an input end for receiving an input voltage, an output end for outputting an output voltage, a switch unit for controlling an electrical connection between the input end and the output end according to a control signal, a protection unit for generating the control signal according to an input current passing through the input end, and a first parasitic transistor for controlling an electrical connection between a second end and a third end according to the control signal, wherein when the input current is greater than a threshold value, the switch unit turns off electrical connection between the input end and the output end according to the control signal, and the first parasitic transistor turns on electrical connection between the second end and the third end of first parasitic transistor according to the control signal to reduce variation of input current. | 07-12-2012 |
20130163136 | Overcurrent Detection Circuit and Overcurrent Detection Method - An overcurrent detection circuit for a DC-to-DC power converter is disclosed. The overcurrent detection circuit includes a dynamic reference unit for outputting a dynamic reference signal, a load current measurement unit for measuring a load current of the DC-to-DC power converter to output a measurement signal, and a first comparator including a positive input terminal coupled to the load current measurement unit, a negative input terminal coupled to the dynamic reference unit and an output terminal coupled to an overcurrent protection device for outputting an overcurrent protection signal to activate the overcurrent protection device when the measurement signal is greater than the dynamic reference signal. | 06-27-2013 |
20130181685 | Charging Circuit for Capacitor - A charging circuit for a capacitor includes a current mirror module including a first branch circuit, a second branch circuit and a third branch circuit for supplying a plurality of output currents respectively, a switching module coupled to the first branch circuit and the second branch circuit for determining a conducting condition of the switching module according to the plurality of output currents from the first branch circuit and the second branch circuit, and an active loading circuit coupled to the third branch circuit and the switching module for adjusting a current passing through the active loading circuit according to the conducting condition of the switching module. The capacitor has one end coupled to the first branch circuit and the switching module to process a charging operation according to the output current of the first branch circuit. | 07-18-2013 |
20140070776 | Switching Regulator - A switching regulator for outputting an output voltage is disclosed. The switching regulator includes an upper gate switch, for turning on and turning off according to an upper gate control signal; a lower gate switch, coupled to the upper gate switch, for turning on and turning off according to a lower gate control signal; and a logic circuit, for generating the lower gate control signal according to a lower gate off signal. The lower gate switch turns off during an activation period of the switching regulator. | 03-13-2014 |
20140097811 | CURRENT-LIMIT SYSTEM AND METHOD - A current-limit system for limiting an average current of an output signal of a DC-DC converter includes a current sensing device, coupled to the DC-DC converter, for detecting the average current of the output signal of the DC-DC converter; and a current-to-voltage converting module, coupled to the current sensing device, for converting the average current into a clamp voltage, in order to control the DC-DC converter according to the clamp voltage. | 04-10-2014 |
Patent application number | Description | Published |
20090259921 | METHOD AND APPARATUS FOR DECODING SHORTENED BCH CODES OR REED-SOLOMON CODES - The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied. | 10-15-2009 |
20100031113 | METHOD AND APPARATUS OF CANDIDATE LIST AUGMENTATION FOR CHANNEL CODING SYSTEM - The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems. | 02-04-2010 |
20110185000 | Method for carry estimation of reduced-width multipliers - A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics. | 07-28-2011 |
20130111304 | CYCLIC CODE DECODING METHOD AND CYCLIC CODE DECODER | 05-02-2013 |
20140095960 | FULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEM - A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture. | 04-03-2014 |
Patent application number | Description | Published |
20090191616 | Biosensor structure and fabricating method thereof - A biosensor structure and a method for fabricating the same are described. The biosensor structure for detecting at least a single cell includes a substrate with an insulating surface, a conductive layer and a plurality of capture molecules. The conductive layer is disposed on the substrate, and has a first pattern and a second pattern separated from each other. The first pattern includes a plurality of first finger configurations, and the second pattern includes a plurality of second finger configurations, so as to form interdigitated array. The capture molecules are immobilized on the conductive layer, such that the cell that is bound specifically to the capture molecules on two adjacent first and second finger configurations is detected. The biosensor structure is feasible for real-time (<3 min), specific, and quantitative targeted cell detection down to a single cell. | 07-30-2009 |
20120043209 | MICROFLUIDIC CONTROL APPARATUS AND OPERATING METHOD THEREOF - A microfluidic control apparatus and operating method thereof. The microfluidic control apparatus includes a photoconductive material layer and a flow passage. When a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes are formed on the photoconductive material layer according to the specific optical pattern. The at least three virtual electrodes include a first virtual electrode, a second virtual electrode and a third virtual electrode disposed beside the first virtual electrode. There is a specific proportion among a distance between first virtual electrode and third virtual electrode, a width of first virtual electrode, a distance between first virtual electrode and second virtual electrode, and a width of second virtual electrode. When the specific optical pattern changes, the at least three virtual electrodes also change to generate an electro-osmotic force to control the moving state of a microfluid in a flow passage. | 02-23-2012 |
20140034499 | MICROFLUIDIC CONTROL APPARATUS AND OPERATING METHOD THEREOF - A microfluidic control apparatus operating method is disclosed. The microfluidic control apparatus operating method is applied in a microfluidic control apparatus, and the microfluidic control apparatus includes a photoconductive material layer and a flow passage. The microfluidic control apparatus operating method includes steps of (a) when a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes being formed on the photoconductive material layer according to the specific optical pattern; (b) when the specific optical pattern changes, the at least three virtual electrodes also changing to generate an electro-osmotic force to control a moving state of a microfluid in the flow passage. | 02-06-2014 |
Patent application number | Description | Published |
20080253080 | PANEL-TYPE HEAT SINK MODULE - The panel-type heat sink module combines the heat-conducting panel, fin heat sink, diversion tank, fan and heat pipe into a single module. There is a heat-conducting surface and an assembly surface of the heat-conducting panel. The fin heat sink is assembled onto the assembly surface. The diversion tank is adapted onto the assembly surface and located nearby the fin heat sink. The diversion tank includes a fan container and a diversion channel. The fan is assembled into the fan container, and the heat pipe is assembled between the assembly surface and the fin heat sink. The heat pipe penetrates through the diversion tank; thus, the heat sources guided by the heat-conducting panel will be uniformly guided into the fin heat sink and diversion tank via the heat pipe. An air stream generated by the fan flows towards the fin heat sink, improving heat-radiation, and reducing assembly space. | 10-16-2008 |
20110315359 | RADIATOR FAN MODULE - A radiator fan module has a fan assembly, cooling fin and heat conductor. The fan assembly has a shell seat and fan blade, an air outlet is set at one side of the shell seat, the cooling fin is set correspondingly to the outlet, and the cooling end of the conductor is mated with the fin. The outlet forms an inward extended wall, an outward extended wall and an extended inner space set between the outlet and fan blade. The outlet has a width-reducing pattern. A notched space is formed externally between the inward extended wall and shell seat. An inward extended heat conductor is formed by the extension of the inner end of the cooling fin and is located within the range of the extended inner space, and provided with a blade corresponding side that is located correspondingly to a peripheral position of the blade. | 12-29-2011 |
20130174966 | MOLDING METHOD OF A HEAT PIPE FOR CAPILLARY STRUCTURE WITH CONTROLLABLE SINTERING POSITION - A molding method of the heat pipe for capillary structure with controllable sintering position wherein said heat pipe is fabricated by said pipe body, grid-sintered composite capillary structure, core rod, evaporation section sintered capillary structure and powder limiting grid. This allows fabrication of the evaporation section sintered capillary structure with the help of the powder limiting grid, such that the capillary structure could be molded more easily while controlling accurately the sintering position and range. Moreover, with embedding of said grid-sintered composite capillary structure, the steam flow channel of the heat pipe could be further expanded and adapted to the flexible processing of the pipe wall, thus facilitating the fabrication and improving the vaporization efficiency of the working fluid with better applicability and industrial benefits. | 07-11-2013 |
Patent application number | Description | Published |
20090321875 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer. | 12-31-2009 |
20100087054 | METHOD FOR FORMING DEEP WELL OF POWER DEVICE - The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer. | 04-08-2010 |
20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 07-29-2010 |
20100276810 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate. | 11-04-2010 |
20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 01-05-2012 |
20120175727 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 07-12-2012 |
20150069503 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an active region is disclosed. A field-plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field-plate region. At least one trench-gate structure is disposed in the substrate corresponding to the bulk region. At least one source-doped region is in the substrate corresponding to the bulk region, wherein the source-doped region surrounds the trench-gate structure. A drain-doped region is in the substrate at a second side opposite to the first side of the field-plate region, wherein an extending direction of length of the trench-gate structure is perpendicular to that of the drain-doped region as viewed from a top view perspective. | 03-12-2015 |
Patent application number | Description | Published |
20090041088 | METHODS AND APPARATUSES FOR CHANNEL ASSESSMENT - An embodiment of an apparatus for channel assessment is provided, comprising a radio frequency (RF) unit, a baseband unit and a microprocessor control unit (MCU). The baseband unit coupling to the RF unit directs the RF unit to selectively hop into one of a plurality of available channels in a frequency band using a pseudorandom sequence to receive a plurality of packets via the hopped channel. The MCU coupling to the baseband unit accumulates a measure for the hopped channel according to reception results of the packets and marks the hopped channel as a bad channel when the accumulated measure exceeds a predetermined threshold. The measure represents the inaccuracy extent during packet reception via the hopped channel. | 02-12-2009 |
20110075778 | METHODS FOR CONTROLLING A MAIN CLOCK SOURCE SHARED BETWEEN DIFFERENT WIRELESS COMMUNICATIONS MODULES AND APPARATUSES USING THE SAME - A communications apparatus is provided. A first wireless communications module provides a first wireless communications service and communicates with a first communications device in compliance with a first protocol. A second wireless communications module provides a second wireless communications service and communicates with a second communications device in compliance with a second protocol. A clock source is shared by the first and the second communications modules and provides a reference clock to the first and the second communications modules. The first wireless communications module detects a request from the second wireless communications module for activating the clock source, determines whether the reference clock has been stably generated by the clock source, and adjusts an electrical characteristic of the clock source to facilitate the reference clock output from the clock source to achieve a target frequency when the reference clock has not been stably generated. | 03-31-2011 |
20110076945 | Methods for Controlling a Main Clock Source Shared Between Different Wireless Communication Modules and Apparatuses Using the Same - A wireless communications module coexisting with a wireless telephony communications module includes a radio frequency (RF) module, a MODEM, a clock generator and distributor and a system control logic. The system control logic issues an external interrupt (EINT) signal to the wireless telephony communications module for activating a clock source via the wireless telephony communications module. When the clock source is activated, the clock generator and distributor receives a reference clock from the activated clock source, converts the reference clock into one or more internal clocks and drives the internal clock or clocks to the RF module and the MODEM for synchronization therebetween. | 03-31-2011 |
Patent application number | Description | Published |
20110161084 | APPARATUS, METHOD AND SYSTEM FOR GENERATING THRESHOLD FOR UTTERANCE VERIFICATION - Apparatus, method and system for generating a threshold for utterance verification are introduced herein. When a processing object is determined, a recommendation threshold is generated according to an expected utterance verification result. In addition, extra collection of corpuses or training models is not necessary for the utterance verification introduced here. The processing unit can be a recognition object or an utterance verification object. In the apparatus, method and system for generating a threshold for utterance verification, at least one of the processing objects is received and then a speech unit sequence is generated therefrom. One or more values corresponding to each of the speech unit of the speech unit sequence are obtained accordingly, and then a recommendation threshold is generated based on an expected utterance verification result. | 06-30-2011 |
20120034581 | LANGUAGE LEARNING SYSTEM, LANGUAGE LEARNING METHOD, AND COMPUTER PROGRAM PRODUCT THEREOF - A language learning system including a storage module, a feature extraction module, and an assessment and diagnosis module is provided. The storage module stores training data and an assessment decision tree generated according to the training data. The feature extraction module extracts pronunciation features of a pronunciation given by a language learner. The assessment and diagnosis module identifies a diagnosis path corresponding to the pronunciation of the language learner in the assessment decision tree and outputs feedback information corresponding to the diagnosis path. Thereby, the language learning system can assess and provide feedback information regarding words, phrases or sentences pronounced by the language learner. | 02-09-2012 |
Patent application number | Description | Published |
20100168220 | PLANT EXTRACT COMPOSITION FOR TREATING HEPATITIS C - The invention provides a plant extract composition for treating hepatitis C, including an effective amount of the proanthocyanidins oligomer extracted from a plant material, and a pharmaceutically acceptable carrier or salt, wherein the structure of proanthocyanidins is shown as follows: | 07-01-2010 |
20100168221 | PHARMACEUTICAL COMPOSITION FOR TREATING HEPATITIS B VIRUS AND HEALTH FOOD PRODUCT HAVING HEPATITIS B VIRUS INHIBITING EFFECTS - The invention provides a pharmaceutical composition for treating hepatitis B, including: an effective amount of proanthocyanidins; and a pharmaceutically acceptable carrier or salt, wherein a formula of the monomer of the proanthocyanidins is shown in the following: | 07-01-2010 |
20100317637 | ANTI-HEPATITIS C COMPOSITION AND METHOD FOR PREPARING DRUG FOR INHIBITING HEPATITIS C VIRUSES OR TREATING HEPATITIS C - The invention provides an anti-hepatitis C composition including: an effective amount of limonoid compound, wherein the structure of the limonoid compound is shown as Structure (I): | 12-16-2010 |
20110158933 | LIVER FUNCTION AND TREATMENT OF LIVER DISEASE - A pharmaceutical preparation containing polymeric compounds as shown in the specification. This preparation can be used to improve liver function and treat liver disease, and promoting liver tissue regeneration. | 06-30-2011 |
20120165279 | PHARMACEUTICAL COMPOSITION AND METHOD FOR PREVENTING OR TREATING HEPATITIS C - A pharmaceutical composition for preventing or treating hepatitis C is provided, including oleanolic acid derivatives as an active ingredient and a pharmaceutically acceptable carrier. A method for preventing or treating hepatitis C in a subject in need thereof is also provided by administering the subject the pharmaceutical composition given above. | 06-28-2012 |
20130123204 | METHOD FOR TREATING HEPATITIS B - The disclosure provides a method for treating hepatitis B, including: administering an effective amount of proanthocyanidins wherein the formula of a monomer of the proanthocyanidins is shown as Formula (I): | 05-16-2013 |
20130150435 | METHOD FOR TREATING HEPATITIS C - The disclosure provides a method for treating hepatitis C, including: administering an effective amount of a proanthocyanidins oligomer to a subject in need, wherein the structure of the proanthocyanidins oligomer is shown as Formula (I): | 06-13-2013 |
20140179774 | METHODS FOR INHIBITION OF SHC-1/P66 TO COMBAT AGING-RELATED DISEASES - The present invention relates to methods of treating one or more symptoms of a SHC-1/p66-related disease, inhibiting ROS generation or for the manufacture of a medicament in the above-mentioned treatment. | 06-26-2014 |
Patent application number | Description | Published |
20090198486 | HANDHELD ELECTRONIC APPARATUS WITH TRANSLATION FUNCTION AND TRANSLATION METHOD USING THE SAME - A handheld electronic apparatus with a translation function comprises an image-capturing device, an image recognition device, a language translator and a display device. The image-capturing device, e.g., a digital camera, is configured to take an image having a text portion of one or more words or sentences, and the image may be shown on the display device. The image recognition device is configured to recognize the text portion to be in a first language. For example, the recognition uses optical character recognition (OCR) technology. The language translator is configured to translate the text portion in the first language into a second language, and the text portion in the second language is shown on the display device. | 08-06-2009 |
20110121875 | POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF - A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal. | 05-26-2011 |
20120248438 | FAULT-TOLERANT UNIT AND METHOD FOR THROUGH-SILICON VIA - A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV | 10-04-2012 |
20140351616 | VOLTAGE-CONTROLLABLE POWER-MODE-AWARE CLOCK TREE, AND SYNTHESIS METHOD AND OPERATION METHOD THEREOF - A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers. | 11-27-2014 |
20150026490 | CLOCK TREE IN CIRCUIT AND OPERATION METHOD THEREOF - A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively. | 01-22-2015 |
Patent application number | Description | Published |
20100029166 | FABRICATION METHOD OF DISCHARGE LAMP - A fabrication method for discharge lamps is disclosed, which comprises providing a glass tube of diameter between 2 and 20 mm, the glass tube having an inner wall coated with a fluorescent phosphor and having a through-passage with a first end and a second end, connecting a first dielectric electrode to the first end of the glass tube by applying an adhesive to a contacted portion of the glass tube and the first dielectric electrode, and sintering the contacted portion of the glass tube and the first dielectric electrode to securely connect the glass tube and the first dielectric electrode. Subsequently, processes of filling and sealing are conducted to complete the fabrication of the discharge lamps. | 02-04-2010 |
20110283741 | TUBE BENDING APPARATUS - A tube bending apparatus for bending a straight lamp tube includes a horizontal heating chamber, a vertical heating chamber and a tube bending mold. The horizontal heating chamber includes a bending tube heating zone and two pre-heating zones. The bending tube heating zone has a working temperature higher than that of the two pre-heating zones. The vertical heating chamber communicates with the horizontal heating chamber and includes a mold heating zone. The mold heating zone has a working temperature higher than or equal to that of the bending tube heating zone. The tube bending mold is heated in the mold heating zone in a working temperature to bend the straight lamp tube held and heated in the horizontal heating chamber. | 11-24-2011 |
20120190253 | LAMP CONNECTION DEVICE - A lamp connection device, which connects with an external circuit and a lamp, comprises an elastic conduction member having at least one engagement section and two winding connection members respectively formed at two ends of the elastic conduction member. The conductive wire of the external circuit and the conductive filament of the lamp are electrically connected to the elastic conduction member via the winding connection members. The engagement section is electrically connected with the conductive wire and conductive filament. Thereby, the lamp can be electrically connected with the external circuit, and the lamp connection device can be bent to flexibly connect to different lamp holders or lamp shades. The serrate structure of the engagement section also can realize invasive electrical connection to prevent increased resistance caused by the oxide layer formed on the surface of the conductive wire. | 07-26-2012 |
20120228652 | LED LAMP AND MANUFACTURING METHOD THEREOF - An LED lamp (Light Emitting Diode) manufacturing method is disclosed. The method includes the steps as following. First, a fluorescent powder and a translucent plastic are mixed to be a mixed material, and the ratio of the fluorescent powder and the translucent plastic is below 80:100. Second, the mixed material is applied to form a lamp shell by the injection molding technology. Third, at least one LED is arranged at the center of the bottom of the lamp shell. | 09-13-2012 |
Patent application number | Description | Published |
20110156838 | MICROWAVE SUPPLYING APPARATUS AND MICROWAVE PLASMA SYSTEM - The invention discloses a microwave supplying apparatus including a microwave generator, a first power divider, a second power divider, a first waveguide, and a second wave guide. The first waveguide is connected to the microwave generator and has a first output terminal and a second output terminal to divide a microwave generated by the microwave generator along a first direction. The second power divider is connected to the first output terminal and has a third output terminal and a fourth output terminal to divide the microwave along a second direction. The first waveguide and the second waveguide are connected to the third output terminal and the fourth terminal respectively and receive the microwave through the first power divider and the second power divider to respectively output the microwave fields with approximate intensity distributions. | 06-30-2011 |
20120111497 | COMPLEX EPOXY RESIN ADHESIVE ADDED WITH CARBON NANOTUBES AND METHOD OF USING THE SAME - The present invention discloses a complex epoxy resin adhesive added with carbon nanotubes, and the complex epoxy resin adhesive can be prepared in advance and then stored at room temperature. When use, the preheating step is no longer required anymore, and the complex epoxy resin adhesive mixed with carbon nanotubes is coated uniformly onto an adhering position, and microwave is used for heating and curing the adhesive, so as to achieve the dual effects of surpassing the enhanced curing property of a simple epoxy resin and reducing the curing time. | 05-10-2012 |
20130175261 | MULTI-SLOT MICROWAVE DEVICE AND PROCESSING SYSTEM THEREOF - A multi-slot resonant microwave device comprises a plurality of slot microwave resonator units and at least one microwave emitting source. Each of the plurality of slot microwave resonator unit is defined as a slot resonant cavity. Whenever at least one of the microwave emitting sources emits microwave power into the plurality of slot microwave resonator units, the plurality of slot microwave resonator units resonate simultaneously, and produce an electromagnetic field with the same polarization direction. Therefore, the multi-slot resonator device can deal with large-area microwave heating with greater microwave effect to shorten operating time and accomplish the objective of homogeneous and megathermal microwave heating. | 07-11-2013 |
Patent application number | Description | Published |
20100089829 | MEMBRANE CLEANING METHOD AND APPARATUS - A membrane cleaning apparatus comprising two electrode plates and a filtration unit is provided, wherein the filtration unit is disposed between the electrode plates. The filtration unit comprises a supporting plate and a membrane, and the membrane is disposed on the support plate. This invention can effectively clean the fouling on the membrane by applying an electric field in the membrane region and performing a back flushing process on the membrane. Moreover, a membrane cleaning method is also provided. | 04-15-2010 |
20100163482 | SYSTEM AND METHOD FOR TREATING AMMONIA-BASED WASTEWATER - A system for treating ammonia-based wastewater is provided. The system includes a first reactor, including: denitrification bacteria for denitrification; a second reactor disposed on the back of the first reactor, wherein the second reactor includes an aerator and aerobic heterotrophic bacteria, and has an HRT of less than 6 hours; a third reactor disposed on the back of the first reactor, wherein the third reactor contains nitrification bacteria carried on the carriers for improving nitrification; and a solid-liquid-separating reactor disposed on the back of the third for separating the solids and liquids in the effluent of the third reactor. | 07-01-2010 |
20120055884 | METHOD AND APPARATUS FOR HYDROLYZING ORGANIC SOLID - A method and an apparatus for hydrolyzing an organic solid are described. The method includes mixing an organic solid and a nanobubble water having a plurality of nanobubbles, to form an organic liquid, in which the nanobubbles contain a combustible gas; and applying an ultrasonic wave on the organic liquid, such that the nanobubbles generate an additional cavitation effect. A preprocessor is applicable to an organic solid processing system having an anaerobic digestion tank, in which the anaerobic digestion tank has anaerobic microbes for generating a combustible gas. The preprocessor includes a nanobubble water generator, a digestion tank, and an ultrasonic wave generator. With the method and the structure, the nanobubbles are used to increase the probability of generation of the additional cavitation effect, and the combustible gas is used to improve an impact force of bursts produced by the cavitation effect. | 03-08-2012 |
Patent application number | Description | Published |
20110124134 | END-CUT FIRST APPROACH FOR CRITICAL DIMENSION CONTROL - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 05-26-2011 |
20110212403 | METHOD AND APPARATUS FOR ENHANCED DIPOLE LITHOGRAPHY - Provided is a lithography system that includes a source for providing energy, an imaging system configured to direct the energy onto a substrate to form an image thereon, and a diffractive optical element (DOE) incorporated with the imaging system, the DOE having a first dipole located in a first direction and a second dipole located in the first direction or a second direction perpendicular the first direction. The first dipole includes a first energy-transmitting region spaced a first distance from a center of the DOE. The second dipole includes a second energy-transmitting region spaced a second distance from the center of the DOE. The first distance is greater than the second distance. | 09-01-2011 |
20120074400 | MULTIPLE EDGE ENABLED PATTERNING - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 03-29-2012 |
20130155381 | METHODS FOR SMALL TRENCH PATTERNING USING CHEMICAL AMPLIFIED PHOTORESIST COMPOSITIONS - A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy. | 06-20-2013 |
20130175629 | DEVICE AND METHODS FOR FORMING PARTIALLY SELF-ALIGNED TRENCHES - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer. | 07-11-2013 |
20130175637 | DEVICE AND METHODS FOR SMALL TRENCH PATTERNING - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers. | 07-11-2013 |
20130295755 | METHODS FOR FORMING TRENCHES - Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask. | 11-07-2013 |
20130323898 | METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER - A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process. | 12-05-2013 |
20140035054 | Device and Methods for Small Trench Patterning - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers. | 02-06-2014 |
20140106479 | End-Cut First Approach For Critical Dimension Control - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 04-17-2014 |
20140199827 | Device and Methods for Small Trench Patterning - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers. | 07-17-2014 |
20140252559 | Multiple Edge Enabled Patterning - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 09-11-2014 |
Patent application number | Description | Published |
20090013192 | INTEGRITY CHECK METHOD APPLIED TO ELECTRONIC DEVICE, AND RELATED CIRCUIT - An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data. | 01-08-2009 |
20090024784 | METHOD FOR WRITING DATA INTO STORAGE ON CHIP AND SYSTEM THEREOF - Disclosed are a method for writing data into a first storage on a chip and a system thereof. The method includes storing an initial firmware into a second storage on the chip, programming the first storage according to a specific data by utilizing the initial firmware, and blocking further programming operations applied to at least part of the specific data after the specific data is successfully stored in the first storage. Therefore the invention can save the external pin connections of the chip to prevent computer hackers from accessing or changing the content of the storage. | 01-22-2009 |
20090327750 | SECURITY SYSTEM FOR CODE DUMP PROTECTION AND METHOD THEREOF - A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks signal communicated between the processor and the storage device to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result. | 12-31-2009 |
20130318363 | SECURITY SYSTEM FOR CODE DUMP PROTECTION AND METHOD THEREOF - A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks the address pattern and the information pattern to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result. | 11-28-2013 |
Patent application number | Description | Published |
20110125001 | 3D MICROELECTRODE STRUCTURE AND METHOD FOR ASSEMBLING THE SAME - The present invention discloses a method for assembling a 3D microelectrode structure. Firstly, 2D microelectrode arrays are stacked to form a 3D microelectrode array via an auxiliary tool. Then, the 3D microelectrode array is assembled to a carrier chip to form a 3D microelectrode structure. The present invention uses an identical auxiliary tool to assemble various types of 2D microelectrode arrays having different shapes of probes to the same carrier chip. Therefore, the method of the present invention increases the design flexibility of probes. The present invention also discloses a 3D microelectrode structure, which is fabricated according to the method of the present invention and used to perform 3D measurement of biological tissues. | 05-26-2011 |
20110141485 | System and Method for Localizing a Carrier, Estimating a Posture of the Carrier and Establishing a Map - Provided is a system for localizing a carrier, estimating a posture of the carrier and establishing a map. The system includes: an inertial measurement device, measuring a motion state and a rotation state of the carrier; a vision measurement device disposed on the carrier for picturing an environment feature in an indoor environment where the carrier locates; and a controller receiving measuring results from the inertial measurement device and the vision measurement device to estimate a posture information, a location information and a velocity information of the carrier, and establishing a map having the environment feature. The controller estimates based on a corrected measuring result from one of the inertial measurement device and the vision measurement device, then controls the other one of the inertial measurement device and vision measurement device to measure, and accordingly corrects the posture, location and velocity information of the carrier and the map. | 06-16-2011 |
20110144467 | FLEXIBLE 3D MICROPROBE STRUCTURE - The present invention discloses a flexible 3D microprobe structure, which comprises at least one probe, a base and a hinge portion. The probe is connected to the base via the hinge portion. The probe forms a bend angle with respect to a normal of the base by attracting the probe through an electrostatic force to make the hinge portion bend with respect to the base, and thus to form a 3D structure having the bend angle. The probe, the base and the hinge portion are made of a flexible polymeric material to reduce the inflammation response of creatures. Further, a fixing element is used to enhance the structural strength of the flexible 3D microprobe structure. | 06-16-2011 |
20110235865 | ADJUSTABLE RANGE FINDER AND THE METHOD THEREOF - An adjustable range finder and the method thereof are disclosed, in which the method comprising: projecting a first beam containing information of an object on a refractive optical element, being comprised a liquid-crystal layer, electrically connected to a voltage device, and a transmission blazed grating, so as to generate a second beam; enabling the voltage device to provide a first voltage to the liquid-crystal layer for forming an energy-concentrated M | 09-29-2011 |
20120229311 | DEVICE AND METHOD FOR COMPRESSING FEATURE DESCRIPTOR - A method and a device for compressing a feature descriptor are disclosed. The device includes a non-uniform quantizer and a run-length encoder. The non-uniform quantizer accesses a source feature descriptor from a storage device, and non-uniformly quantizes the source feature descriptor having source vectors into an intermediate feature descriptor having intermediate vectors according to a vector default value. The run-length encoder executes run-length coding for the intermediate feature descriptor to generate a compressed feature descriptor. | 09-13-2012 |
20130064452 | APPARATUS AND METHOD FOR PROCESSING IMAGE FEATURE DESCRIPTOR - An apparatus and a method for processing image feature descriptor are disclosed. The image feature descriptor processing apparatus comprises a header storing unit, a vector storing unit, a feature capture unit, a distribute unit, and a memory controller. The feature capture unit captures image feature descriptors. The distribute unit generates a header base address, a vector base address, headers, and vectors according to the image feature descriptors. The memory controller continuously writes the headers to the header storage unit according to the header base address and continuously writes the vectors to the vector storage unit according to the vector base address. | 03-14-2013 |
20130243330 | METHOD AND APPARATUS FOR CONSTRUCTING IMAGE BLUR PYRAMID, AND AN IMAGE FEATURE EXTRACTING CIRCUIT - A method and an apparatus for constructing an image blur pyramid, and an image feature extracting circuit are disclosed. The image blur pyramid construction apparatus comprises a first image blur circuit, a second image blur circuit and an image sub-sampler. The first image blur circuit and the second image blur circuit simultaneously generate a first interval and a second interval in the same octave according to an input image, a first filter and a second filter. The dimension of the second filter is greater than that of the first filter. The image sub-sampler couples with the second image blur circuit and down samples the second interval to generate a sub-sample image. | 09-19-2013 |
Patent application number | Description | Published |
20100039908 | AUTOMATIC POWER CONTROL SYSTEM FOR OPTICAL DISC DRIVE AND METHOD THEREOF - A method for calibrating an initial driving signal for driving an optical pick-up head of an optical disk drive is provided. On one embodiment, said optical disk drive is utilized for reading or writing data on an optical disk, the optical disk comprises a plurality of auto power control areas (APC areas) and a plurality of data areas, and the APC areas and the data areas are interleaved in between. First, in the APC areas, an initial driving signal is used to drive the optical pick-up head to emit laserbeam. A detected level of the laserbeam is then obtained. An update initial driving signal is then calibrated according to the detected level and a target level. | 02-18-2010 |
20100177614 | METHOD AND APPARATUS FOR WRITING DATA TO OPTICAL STORAGE MEDIUM - A method and apparatus for writing data to an optical storage medium are disclosed. A write signal indicating power levels of a laser diode is generated by encoding and decoding codewords. The codewords are generated and decoded according to a Successive State Change Criterion (SSCC) or SSCC II proposed by the present invention. By doing so, toggling (i.e. state changing) times occurring in channels transferring the codewords can be significantly reduced to avoid the problems of pulse distortion and disappearance in high frequency transmission. Alternatively, toggles appearing in the respective channels can be spread to avoid interference between the channels. Further, a phase adjustment device for adjusting a phase of each codeword is disclosed. | 07-15-2010 |
20110188363 | Automatic Power Control System for Optical Disc Drive and Method Thereof - A method and system for calibrating an initial driving signal for driving an optical pick-up head of an optical disk drive is provided. On one embodiment, said optical disk drive is utilized for reading or writing data on an optical disk, the optical disk includes a plurality of auto power control areas (APC areas) and a plurality of data areas, and the APC areas and the data areas are interleaved in between. In at least one of the APC areas that before the data areas for a normal data writing, an initial driving signal is used for the normal data writing to drive the optical pick-up head to emit laserbeam. A detected level of the laserbeam is then obtained. An update initial driving signal is then calibrated according to the detected level and a target level. | 08-04-2011 |
20120039157 | METHOD FOR RECORDING CRITICAL PATTERNS WITH DIFFERENT MARK LENGTHS ONTO OPTICAL STORAGE MEDIUM AND RELATED CONTROLLER THEREOF - An exemplary method for recording a first mark with a first length and a second mark with a second length onto an optical storage medium includes: when recording of the first mark requires a power transition from a first laser power level to a second laser power level, making a specific control signal have a logic transition from a low logic value to a high logic value and other control signals have no logic transition; and when recording of the second mark requires a power transition from a third laser power level to a fourth laser power level, making the specific control signal have the logic transition from the low logic value to the high logic value and other control signals have no logic transition. | 02-16-2012 |
20120163146 | METHOD AND APPARATUS FOR WRITING DATA TO OPTICAL STORAGE MEDIUM - A method and apparatus for writing data to an optical storage medium are disclosed. A write signal indicating power levels of a laser diode is generated by encoding and decoding codewords. The codewords are generated and decoded according to a specific requirement proposed by the present invention. By doing so, toggling (i.e. state changing) times occurring in channels transferring the codewords can be significantly reduced to avoid the problems of pulse distortion and disappearance in high frequency transmission. Alternatively, toggles appearing in the respective channels can be spread to avoid interference between the channels. Further, a phase adjustment device for adjusting a phase of each codeword is disclosed. | 06-28-2012 |
20130099835 | CALIBRATION APPARATUS FOR PERFORMING PHASE DETECTION/EDGE DISTANCE DETECTION UPON SIGNALS AND RELATED CALIBRATION METHOD THEREOF - An exemplary calibration apparatus includes a detecting circuit and a calibrating circuit. The detecting circuit is arranged for generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge. The calibrating circuit is coupled to the detecting circuit, and arranged for calibrating at least one of the signal sources according to the detection result. An exemplary calibration method includes the following steps: generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge; and calibrating at least one of the signal sources according to the detection result. | 04-25-2013 |