Patent application number | Description | Published |
20100024969 | PROTECTIVE COVER SHEET COMPRISING A UV-ABSORBING LAYER FOR A POLARIZER PLATE AND METHOD OF MAKING THE SAME - The invention relates to a protective cover sheet comprising a low birefringence protective polymer film and a layer that promotes adhesion to poly(vinyl alcohol), the protective cover sheet comprising at least one functional layer containing a UV-absorbing polymer. | 02-04-2010 |
20100302292 | AQUEOUS COMPOSITIONS WITH IMPROVED SILICON CORROSION CHARACTERISTICS - A process for printing inkjet ink and other aqueous compositions through silicon-based microelectromechanical printer structures is disclosed that suppresses the normal dissolution of the silicon device components in contact with the aqueous composition. Inkjet ink and other aqueous compositions used in the process contain the soluble salts of organic aromatic azo compounds in sufficient concentrations to inhibit silicon corrosion. The useful lifetime of microelectromechanical fluidic devices based on silicon fabrication is extended. | 12-02-2010 |
20100304028 | CONTINUOUS INK JET INK COMPOSITIONS - The invention relates to continuous ink jet printing of an aqueous pigmented ink composition recycled from a main ink supply reservoir, employing a printer with a fluid delivery system capable of measuring the ink electrical resistivity, and providing needed quantities of either vehicle replenisher fluid or fresh ink to maintain the desired recycled ink concentration. The electrical resistivity of the pigmented ink can be modified advantageously for stable ink recycling by the addition of the organic amine salt of an acid, and the pH stability of the ink can be simultaneously improved by the additional inclusion of the neutral form of the organic amine in similar molar proportions to the amine salt. The pigmented ink jet ink compositions provide for particularly stable and invariant fluid properties during periods of extended printer operation and ink recirculation. | 12-02-2010 |
20110123714 | CONTINUOUS INKJET PRINTER AQUOUS INK COMPOSITION - A continuous ink jet printer aqueous ink composition including pigment particles dispersed with a dispersant or self dispersing pigment particles without the need for a dispersant, and a polymer additive distinct from any dispersant used to disperse the pigment particles, wherein the polymer additive comprises a water soluble block copolymer having one or more poly(ethylene oxide) block segments wherein the polymer additive is present in an amount effective to stabilize the ink composition against shear induced agglomeration caused by pumping the ink composition through a continuous ink jet printing fluid system. A method of continuous ink jet printing includes A) providing a main fluid supply of a continuous inkjet printer with an aqueous ink composition of the invention; B) pumping the ink composition from the main fluid supply to a print head and ejecting a continuous stream of the ink composition from the print head which continuous stream is broken into spaced droplets; and C) in response to electrical signals received from a control mechanism, controlling the spaced droplets to select between printing droplets for marking a substrate and nonprinting droplets that are collected and returned to the main fluid supply. | 05-26-2011 |
20140216784 | MAKING A CONDUCTIVE ARTICLE HAVING MICRO-CHANNELS - A method of making a conductive article includes providing a substrate having a surface with one or more micro-channels having a width of less than 12 μm. A composition is provided over the substrate and in the one or more micro-channels. The composition includes water and silver nanoparticles dispersed in the water and he weight percentage of silver in the composition is greater than 70% and the viscosity of the composition is in a range from 10 to 10,000 centipoise. The composition is removed from the surface of the substrate. The composition provided in the micro-channels is dried and converted to form one or more electrically conductive micro-wires. | 08-07-2014 |
20140216797 | CONDUCTIVE ARTICLE HAVING MICRO-CHANNELS - A conductive article includes a substrate having a micro-channel. A metal nanoparticle composition is formed in the micro-channel. The metal nanoparticle composition includes silver nanoparticles and a polymer having both carboxylic acid and sulfonic acid groups. | 08-07-2014 |
20140220259 | MAKING A CONDUCTIVE ARTICLE - A method of making a conductive article includes depositing on a substrate a metal nanoparticle composition having water, silver nanoparticles dispersed in the water and a water-soluble polymer having both carboxylic acid and sulfonic acid groups. The weight percentage of silver in the composition is greater than 10%. The metal nanoparticle composition is dried. The dried metal nanoparticle composition is converted to improve the electrical conductivity of the dried metal nanoparticle composition. | 08-07-2014 |
20140220366 | CONDUCTIVE ARTICLE HAVING SILVER NANOPARTICLES - A conductive article includes a metal nanoparticle composition formed on a substrate. The metal nanoparticle composition includes silver nanoparticles and a polymer having both carboxylic acid and sulfonic acid groups. The weight ratio of the polymer to silver is 0.0005 to 0.04. | 08-07-2014 |
20140221543 | SILVER METAL NANOPARTICLE COMPOSITION - A metal nanoparticle composition includes water and a water-soluble polymer having both carboxylic acid and sulfonic acid groups. Silver nanoparticles are dispersed in the water such that the weight percentage of silver in the composition is greater than 10%. | 08-07-2014 |
20140239504 | MULTI-LAYER MICRO-WIRE STRUCTURE - A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the substrate surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel. | 08-28-2014 |
20140242297 | MAKING MULTI-LAYER MICRO-WIRE STRUCTURE - A method of making a multi-layer micro-wire structure includes providing a substrate having a surface and forming a plurality of micro-channels in the surface. A first material composition is located in a first layer only in each micro-channel and not on the surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel. | 08-28-2014 |
20140292951 | INKJET RECEIVER PRECOATS INCORPORATING SILICA - An inkjet receiving media comprising a substrate having a transparent topmost layer coated thereon at solid content of from 0.3 to 2.5 g/m | 10-02-2014 |
20140322436 | MAKING MULTI-LAYER MICRO-WIRE STRUCTURE - A method of making a multi-layer micro-wire structure includes providing a substrate having a surface and forming a plurality of micro-channels in the surface. A first material composition is located in a first layer only in each micro-channel and not on the surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel. | 10-30-2014 |
Patent application number | Description | Published |
20110101309 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 05-05-2011 |
20110108802 | Metal-Free Integrated Circuits Comprising Graphene and Carbon Nanotubes - An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene. | 05-12-2011 |
20110108943 | HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation. | 05-12-2011 |
20110114918 | FABRICATION OF GRAPHENE NANOELECTRONIC DEVICES ON SOI STRUCTURES - A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer. | 05-19-2011 |
20110115021 | ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX - Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion. | 05-19-2011 |
20110115553 | SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE - SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. | 05-19-2011 |
20110127438 | Dosimeter Powered by Passive RF Absorption - A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency. | 06-02-2011 |
20110171792 | BACK-GATED FULLY DEPLETED SOI TRANSISTOR - A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner. | 07-14-2011 |
20120112166 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 05-10-2012 |
20120115295 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 05-10-2012 |
20120181505 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 07-19-2012 |
20120326129 | METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES - An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene. | 12-27-2012 |
20130001518 | FABRICATION OF GRAPHENE NANOELECTRONIC DEVICES ON SOI STRUCTURES - A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer. | 01-03-2013 |
20130015912 | SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE - SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. | 01-17-2013 |
20130026544 | FULLY DEPLETED SILICON ON INSULATOR NEUTRON DETECTOR - A method for forming a neutron detector comprises thinning a backside silicon substrate of a radiation detector; and forming a neutron converter layer on the thinned backside silicon substrate of the radiation detector to form the neutron detector. The neutron converter layer comprises one of boron-10 ( | 01-31-2013 |
20130140634 | METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts. | 06-06-2013 |
20130320303 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 12-05-2013 |
20140015051 | METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts. | 01-16-2014 |
20140027871 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 01-30-2014 |
20140030838 | CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS - A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor. | 01-30-2014 |
20140070107 | ULTRA-SENSITIVE RADIATION DOSIMETERS - An apparatus comprises a conducting substrate layer, a dielectric layer formed over the conducting substrate layer, a channel formed over at least a portion of the dielectric layer and first and second source/drain regions formed on respective first and second portions of the channel. The channel comprises a thin-film carbon material. The conducting substrate layer, the dielectric layer, the channel and the first and second source/drain regions are configured such that exposure to radiation causes a change in a threshold voltage of the apparatus. | 03-13-2014 |
20140084301 | LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR RADIATION DOSIMETER - A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure. A method for radiation dosimetry includes providing a radiation dosimeter, where the radiation dosimeter includes a lateral silicon-on-insulator bipolar junction transistor having a buried insulator layer; exposing the radiation dosimeter to ionizing radiation; determining a change in one of the collector current and current gain of the radiation dosimeter; and determining an amount of the radiation dose based on the change in one of the collector current and current gain. | 03-27-2014 |
20140088401 | Method For Radiation Monitoring - A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure. A method for radiation dosimetry includes providing a radiation dosimeter, where the radiation dosimeter includes a lateral silicon-on-insulator bipolar junction transistor having a buried insulator layer; exposing the radiation dosimeter to ionizing radiation; determining a change in one of the collector current and current gain of the radiation dosimeter; and determining an amount of the radiation dose based on the change in one of the collector current and current gain. | 03-27-2014 |
20140252500 | SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE - At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening. | 09-11-2014 |
20140252501 | SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE - At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening. | 09-11-2014 |
20140312395 | SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening. | 10-23-2014 |
20140312397 | SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening. | 10-23-2014 |
20140353726 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
20140357043 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
20150035060 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other. | 02-05-2015 |
20150044870 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A SELF-ALIGNED OPL REPLACEMENT CONTACT AND PATTERNED HSQ AND A SEMICONDUCTOR DEVICE FORMED BY SAME - A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity. | 02-12-2015 |
20150048428 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME - A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area. | 02-19-2015 |