Koji Fukuda
Koji Fukuda, Huchu JP
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20110001588 | WAVEFORM EQUALIZATION CIRCUIT WITH PULSE WIDTH MODULATION - There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC | 01-06-2011 |
Koji Fukuda, Kawasaki-Shi JP
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20100175965 | PALLET MONITORING SYSTEM AND MONITORING METHOD - According to one embodiment, a pallet monitoring system for monitoring pallets sequentially conveyed to stations provided along a conveyor path, the system includes: a monitor, connected to the stations. The monitor includes: a defect information collector configured to collect defect information on a defect occurring in the stations; an information storage module configured to store therein the defect information and identification information of the pallets; and a pallet identifier configured to identify the pallets causing a defective product based on the defect information and the identification information stored in the information storage module. | 07-15-2010 |
Koji Fukuda, Fuchu JP
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20080204100 | Logic circuit - For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit. | 08-28-2008 |
20090033431 | Oscillation Circuit - The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO | 02-05-2009 |
20090207957 | Clock recovery circuit - A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value. | 08-20-2009 |
20090232265 | Clock data recovery circuit - A clock data recovery circuit that supplies stable reproduction clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2π. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reproduction clock. | 09-17-2009 |
20100054760 | Phase Detector Circuit for Clock and Data Recovery Circuit and Optical Communication Device Having the Same - A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLK | 03-04-2010 |
20110193595 | OUTPUT DRIVER CIRCUIT - Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN | 08-11-2011 |
Koji Fukuda, Chofu JP
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20120133394 | DATA JUDGMENT/PHASE COMPARISON CIRCUIT - The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC. | 05-31-2012 |
20120249217 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND | 10-04-2012 |
Koji Fukuda, Hanno-Shi JP
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20120319854 | METHOD OF MEASURING CONTACT FAILURE AND CONTACT FAILURE MEASURING DEVICE - In the disclosed method of measuring contact failure and contact failure measuring device, the magnitude of the excessive response fluctuation of the inductive magnetic field around a harness under measurement when an external force is applied to a terminal fitting part of the harness is detected by a magnetic sensor, and the result is displayed as an index of the quality of the contact state of the terminal fitting part. | 12-20-2012 |
Koji Fukuda, Osaka-Shi JP
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20130284260 | Back Electrode Type Solar Cell, Back Electrode Type Solar Cell With Interconnection Sheet, Solar Cell Module, Method of Manufacturing Back Electrode Type Solar Cell With Interconnection Sheet, and Method of Manufacturing Solar Cell Module - A back electrode type solar cell in which a no-electrode-formed region where no electrode is placed is provided in a part of a peripheral portion of a back surface of the back electrode type solar cell such that a line connecting end portions of a plurality of electrodes to one another includes a partially inwardly recessed region and the no-electrode-formed region is located adjacent to each of an electrode for n-type and an electrode for p-type adjacent to each other, a solar cell module, a method of manufacturing a back electrode type solar cell with interconnection sheet, and a method of manufacturing a solar cell module are provided. | 10-31-2013 |
20130298988 | SOLAR BATTERY AND METHOD OF MANUFACTURING SOLAR BATTERY - There is provided a solar battery, including: a solar cell including a porous electrode provided on at least one surface of a substrate; a conductive wire electrically connected to the porous electrode; and an adhesive material provided between the porous electrode and the conductive wire, wherein a part of the adhesive material penetrates into the porous electrode. There is also provided a method of manufacturing the solar battery. | 11-14-2013 |
Koji Fukuda, Hyogo JP
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20140038758 | TENSIONER - A tensioner includes a movable member, a fixed member, biasing means provided between the fixed member and the movable member and configured to bias the movable member along a pressing direction, and a damping member provided between the fixed member and the movable member and configured to damp the pivoting movement of the movable member. The damping member is made of a resin composition whose sliding friction force damps the pivoting movement of the movable member, and a contact angle between the resin composition and water is 70° to 100°, both inclusive. | 02-06-2014 |
Koji Fukuda, Tokyo JP
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20150324482 | NETWORK GRAPH GENERATION METHOD AND DECISION-MAKING ASSISTANCE SYSTEM - A decision-making support system which is a client-server system comprising: multiple servers; a client having a display; a network; and a database. On the basis of data acquisition conditions supplied via the client the multiple servers acquire from the data base on multiple distributed processing platforms, a first data group spanning from the past to the present, and generate a first network graph for the time from the past to the present. The multiple servers also execute multiple simulations based on the first data group, on the basis of provided simulation conditions, and generate second and third network graphs for a time not included in the first data group or for the future. The client receives the results of the generation of these network graphs and displays on the display the first through third network graphs spanning from the past to the present, and to the future, thereby providing the user with a scenario map. | 11-12-2015 |