Patent application number | Description | Published |
20100019341 | BURIED ASYMMETRIC JUNCTION ESD PROTECTION DEVICE - An improved lateral bipolar electrostatic discharge (ESD) protection device ( | 01-28-2010 |
20100244088 | ZENER TRIGGERED ESD PROTECTION - Electrostatic discharge (ESD) protection clamps ( | 09-30-2010 |
20110176244 | ESD PROTECTION DEVICE AND METHOD - An electrostatic discharge (ESD) protection clamp ( | 07-21-2011 |
20120326206 | DEVICES WITH ZENER TRIGGERED ESD PROTECTION - Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided. | 12-27-2012 |
20140061716 | ESD PROTECTION DEVICE - An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp | 03-06-2014 |
20140126091 | Protection Device And Related Fabrication Methods - Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface. | 05-08-2014 |
20140147983 | ESD PROTECTION DEVICE AND METHOD - An electrostatic discharge (ESD) protection clamp ( | 05-29-2014 |
Patent application number | Description | Published |
20120154049 | Common-Mode Feedback Circuit - A differential amplifier circuit with common-mode feedback is disclosed. The amplifier may include a first stage comprising a first differential input configured to drive a first differential pair transistor in a first differential current path, a second differential input configured to drive a second differential pair transistor in a second differential current path, a first differential output, and a second differential output, a second stage comprising a first differential input, a second differential input, a first differential output, and a second differential output, a common-mode feedback circuit, a first conducting element in a first common-mode current path parallel to the first differential current path and comprising a first conducting terminal coupled to the first differential output of the first stage, and a second conducting element in a second common-mode current path parallel to the second differential current path and comprising a first conducting terminal coupled to the second differential output of the first stage. | 06-21-2012 |
20140354308 | INPUT STAGE FOR TEMPERATURE MEASUREMENT SYSTEM - A temperature-measurement input stage is disclosed. In accordance with some embodiments of the present disclosure, a temperature-measurement input stage may comprise a resistor, a thermistor, a first multiplexor, an amplifier, a second multiplexor, and an output stage. The first multiplexor may be configured to couple the resistor to a first amplifier input during a first multiplexor state, and couple the thermistor to the first amplifier input during a second multiplexor state. The amplifier may comprise the first amplifier input, a second amplifier input coupled to a voltage reference, and an amplifier output coupled to a feedback path. The second multiplexor may be configured to route a feedback current to the resistor during the first multiplexor state and route the feedback current to the thermistor during the second multiplexor state. The output stage may be configured to provide an output current based on the feedback current. | 12-04-2014 |
20140355650 | TEMPERATURE MEASUREMENT SYSTEM - A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio. | 12-04-2014 |
20140355651 | CALIBRATED TEMPERATURE MEASUREMENT SYSTEM - In accordance with some embodiments of the present disclosure, a calibrated temperature measurement system comprises a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, and an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal. A memory may comprise resistor-characterization information. A calculation stage communicatively coupled to an ADC output may be configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio and the resistor-characterization information. | 12-04-2014 |
Patent application number | Description | Published |
20100171643 | Techniques for Delay Compensation of Continuous-Time Sigma-Delta Modulators - A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal. | 07-08-2010 |
20100194612 | SWITCHED-CAPACITOR CIRCUITS, INTEGRATION SYSTEMS, AND METHODS OF OPERATION THEREOF - Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur. | 08-05-2010 |
20100207797 | DIGITALLY ADJUSTABLE QUANTIZATION CIRCUIT - Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node. | 08-19-2010 |
20100289538 | CLOCK CONDITIONING CIRCUIT - A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals. | 11-18-2010 |