Patent application number | Description | Published |
20080243739 | Remote Hit Predictor - In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request. | 10-02-2008 |
20090037665 | HIDING CONFLICT, COHERENCE COMPLETION AND TRANSACTION ID ELEMENTS OF A COHERENCE PROTOCOL - According to one embodiment of the invention, an apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution. | 02-05-2009 |
20100023945 | EARLY ISSUE OF TRANSACTION ID - Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor. | 01-28-2010 |
20100262788 | PRE-COHERENCE CHANNEL - A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events. | 10-14-2010 |
20120117330 | METHOD AND APPARATUS FOR SELECTIVELY BYPASSING A CACHE FOR TRACE COLLECTION IN A PROCESSOR - A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed. | 05-10-2012 |
20120144118 | METHOD AND APPARATUS FOR SELECTIVELY PERFORMING EXPLICIT AND IMPLICIT DATA LINE READS ON AN INDIVIDUAL SUB-CACHE BASIS - A method and apparatus are described for selectively performing explicit and implicit data line reads. A controller, located in a cache, individually monitors the data resource availability for each of a plurality of sub-caches also located in the cache. The controller receives a data line request, generates an individual implicit tag request for each of the sub-caches that currently have sufficient data resources to perform an implicit data line read, and generates an individual explicit tag request for each of the sub-caches that do not currently have sufficient data resources to perform an implicit data line read. Each tag request includes an address of the requested data line and an indicator, (represented by at least one bit), of whether the tag request is an explicit or implicit tag request. | 06-07-2012 |
20120144122 | METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION - A method and apparatus for accelerated shared data migration between cores is disclosed. | 06-07-2012 |
20120144124 | METHOD AND APPARATUS FOR MEMORY ACCESS UNITS INTERACTION AND OPTIMIZED MEMORY SCHEDULING - A method and an apparatus for modulating the prefetch training of a memory-side prefetch unit (MS-PFU) are described. An MS-PFU trains on memory access requests it receives from processors and their processor-side prefetch units (PS-PFUs). In the method and apparatus, an MS-PFU modulates its training based on one or more of a PS-PFU memory access request, a PS-PFU memory access request type, memory utilization, or the accuracy of MS-PFU prefetch requests. | 06-07-2012 |
20120159080 | NEIGHBOR CACHE DIRECTORY - A method and apparatus for utilizing a higher-level cache as a neighbor cache directory in a multi-processor system are provided. In the method and apparatus, when the data field of a portion or all of the cache is unused, a remaining portion of the cache is repurposed for usage as neighbor cache directory. The neighbor cache provides a pointer to another cache in the multi-processor system storing memory data. The neighbor cache directory can be searched in the same manner as a data cache. | 06-21-2012 |
20130024829 | METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT - Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state. | 01-24-2013 |
20130077701 | METHOD AND INTEGRATED CIRCUIT FOR ADJUSTING THE WIDTH OF AN INPUT/OUTPUT LINK - A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached. | 03-28-2013 |
Patent application number | Description | Published |
20110177003 | PROTEINS THAT FLUORESCE AT INFRARED WAVELENGTHS OR GENERATE SINGLET OXYGEN UPON ILLUMINATION - This invention provides novel truncation mutants of a phytochrome from the bacterium | 07-21-2011 |
20120134922 | PEPTIDES WHOSE UPTAKE IN CELLS IS CONTROLLABLE - Disclosed herein, in certain embodiments, is a selective transport molecule with increased in vivo circulation. In some embodiments, a selective transport molecule disclosed herein has the formula (A—X—B—C)n—M, wherein C is a cargo moiety; A is a peptide with a sequence comprising 5 to 9 consecutive acidic amino acids, wherein the amino acids are selected from: aspartates and glutamates; B is a peptide with a sequence comprising 5 to 20 consecutive basic amino acids; X is a linker; and M is a macromolecular carrier. | 05-31-2012 |
20120134931 | PEPTIDES WHOSE UPTAKE IN CELLS IS CONTROLLABLE - Disclosed herein, in certain embodiments, is a selective transport molecule with increased in vivo circulation. In some embodiments, a selective transport molecule disclosed herein has the formula (A-X-B-C)-M, wherein C is a cargo moiety; A is a peptide with a sequence comprising 5 to 9 consecutive acidic amino acids, wherein the amino acids are selected from: aspartates and glutamates; B is a peptide with a sequence comprising 5 to 20 consecutive basic amino acids; X is a linker; and M is a macromolecular carrier. | 05-31-2012 |