Patent application number | Description | Published |
20080232167 | Current controlled recall schema - A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell. | 09-25-2008 |
20130170312 | CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST - A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a “time interval test”). | 07-04-2013 |
20160111159 | 10T Non-Volatile Static Random-Access Memory - A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed. | 04-21-2016 |
Patent application number | Description | Published |
20120260117 | Dynamically Tune Power Proxy Architectures - A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted. | 10-11-2012 |
20120330802 | METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE ACCOUNTING - An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. | 12-27-2012 |
20120330803 | METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE THROTTLING - An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value. | 12-27-2012 |
20130145188 | Advanced Pstate Structure with Frequency Computation - A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity. | 06-06-2013 |
20140149750 | COMPUTING SYSTEM VOLTAGE CONTROL - An apparatus including a voltage safety verification unit (VSVU) configured to receive an indication of a first performance state, the first performance state being associated with a first voltage. The first performance state applies to at least one computing system component and the indication is received by a computing system component distinct from the requesting computing system component. The VSVU is configured to receive an indication of a second performance state. The second performance state is associated with a second voltage that is not equal to the first voltage. The VSVU is configured to determine whether the second performance state is within a range defined by a minimum and maximum performance state. Responsive to a determination that the second performance state is within the, the VSVU is configured to set the voltage of the at least one computing system component equal to the voltage associated with the second performance state. | 05-29-2014 |
20140149751 | SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT - A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector. | 05-29-2014 |
20140149752 | ASSOCIATING ENERGY CONSUMPTION WITH A VIRTUAL MACHINE - Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory. | 05-29-2014 |
20140149755 | DECOUPLED POWER AND PERFORMANCE ALLOCATION IN A MULTIPROCESSING SYSTEM - A performance supervisor computer program product is configured to set a maximum and a minimum performance operating limit for a plurality of processing units in accordance with a set of one or more rules enforced by the performance supervisor. Each of the plurality of processing units has logic configured to ensure a request for an operational setting complies with the maximum and minimum operating limits. Each of the plurality of processing units is configured to output a request for a limit compliant operational setting to a performance controller. The performance controller is configured to actuate the operational request. | 05-29-2014 |
20140149762 | DECOUPLED POWER AND PERFORMANCE ALLOCATION IN A MULTIPROCESSING SYSTEM - Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits. | 05-29-2014 |
20140149763 | COMPUTING SYSTEM VOLTAGE CONTROL - Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state. | 05-29-2014 |
20140149769 | COMPUTING SYSTEM FREQUENCY TARGET MONITOR - An apparatus includes memory, a processor coupled to the memory, and a set of one or more frequency target monitors. The processor includes a set of one or more processor cores, and the set of one or more frequency target monitors are coupled to the set of one or more processor cores. Each frequency target monitor is configured to determine a difference between an actual performance and an expected performance of a processor core from the set of one or more processor cores. Each frequency target monitor is also configured to, responsive to determining the difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores, record an indication of a difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores. | 05-29-2014 |
20140149779 | ASSOCIATING ENERGY CONSUMPTION WITH A VIRTUAL MACHINE - Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory. | 05-29-2014 |
20140167832 | CHANGING RESONANT CLOCK MODES - Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver. | 06-19-2014 |
20150061744 | PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS - Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width. | 03-05-2015 |
20150123633 | PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS - Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width. | 05-07-2015 |
20150293844 | BROADCAST AND UNICAST COMMUNICATION BETWEEN NON-COHERENT PROCESSORS USING COHERENT ADDRESS OPERATIONS - Non-address data is received for transmission on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium. | 10-15-2015 |
20150293863 | BROADCAST AND UNICAST COMMUNICATION BETWEEN NON-COHERENT PROCESSORS USING COHERENT ADDRESS OPERATIONS - Non-address data is received that is to be transmitted on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium. | 10-15-2015 |
Patent application number | Description | Published |
20090216998 | Apparatus for and Method of Processor to Processor Communication for Coprocessor Functionality Activation - A novel and useful mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication. | 08-27-2009 |
20150089263 | SYSTEM-WIDE POWER CONSERVATION USING MEMORY CACHE - A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down. | 03-26-2015 |
20150109043 | ADJUSTABLE DELAY CALIBRATION IN A CRITICAL PATH MONITOR - A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section. | 04-23-2015 |
20160132085 | SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT - A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory. | 05-12-2016 |
Patent application number | Description | Published |
20100264232 | METHOD FOR DELIVERING A VOLATILE MATERIAL - A method of delivering a volatile material to the atmosphere in a continuous manner is disclosed. The method includes providing a delivery engine having a reservoir that includes a volatile material mixture. The volatile material mixture includes about 40% to about 100%, by total weight, of the volatile materials each having a vapor pressure at 25° C. of less than about 0.1 torr. The delivery system also includes a microporous membrane enclosing the reservoir, wherein the microporous membrane comprises an average pore size of about 0.01 to about 0.03 microns. | 10-21-2010 |
20100308126 | METHOD FOR DELIVERING A VOLATILE MATERIAL - A method of delivering a volatile material to the atmosphere in a continuous manner is disclosed. The method includes providing a delivery engine having a reservoir that includes a volatile material mixture. The volatile material mixture includes about 40% to about 100%, by total weight, of the volatile materials each having a vapor pressure at 25° C. of less than about 0.1 torr. The delivery system also includes a microporous membrane enclosing the reservoir, wherein the microporous membrane comprises an average pore size of about 0.01 to about 0.03 microns. | 12-09-2010 |
20100308130 | APPARATUS FOR DELIVERING A VOLATILE MATERIAL - An apparatus for delivering a volatile material in a continuous manner is disclosed. The apparatus includes a delivery engine having a reservoir for containing a volatile material; a rupturable substrate secured to the reservoir; a rupture element positioned adjacent to the rupturable substrate; and a breathable membrane enclosing the reservoir, rupturable substrate and rupture element. In some embodiments, the apparatus includes a housing having a notch for compressing the rupture element and breaching the rupturable substrate as it is inserted into the housing. | 12-09-2010 |
20100314461 | VOLATILE COMPOSITION DISPENSER - A volatile composition dispenser comprises a volatile composition container comprising at least one volatile composition therein. A rupture element is positioned proximate to the volatile composition container. The volatile composition container comprises a cam comprising a camming surface. The camming surface is configured to move at least a portion of the rupture element toward the volatile composition container to puncture the volatile composition container and release at least a portion of the volatile composition from the volatile composition container such that the portion of the volatile composition evaporates and exits the volatile composition dispenser. | 12-16-2010 |
20110180621 | APPARATUS FOR DELIVERING A VOLATILE MATERIAL - An apparatus for delivering a volatile material in a continuous manner is disclosed. The apparatus includes a delivery engine having a reservoir for containing a volatile material; a rupturable substrate secured to the reservoir; a rupture element positioned adjacent to the rupturable substrate; and a breathable membrane enclosing the reservoir, rupturable substrate and rupture element. In some embodiments, the apparatus includes a housing having a notch for compressing the rupture element and breaching the rupturable substrate as it is inserted into the housing. | 07-28-2011 |
20130284195 | Applicator Assembly for Applying a Composition - A method for delivering a composition to the scalp including (a) providing a composition in an applicator assembly, the applicator assembly including (i) a container for holding the composition; (ii) an extended tip actuator in fluid communication with the container, the extended tip actuator including (1) a base portion configured to fluidly connect the extended tip actuator to the container; and (2) a body portion configured to fluidly connect the base portion to a hollow tine; and (iii) an engine for delivering the composition from the container through the extended tip actuator; and (b) dispensing the composition from the applicator assembly directly onto the scalp. The tine includes a face located distally from the body portion. The tine includes an aperture in fluid communication with the container. The tine has a protrusion length of from about 0.5 mm to about 100 mm. | 10-31-2013 |
20130284196 | Applicator Assembly for Applying a Composition - A method for delivering a composition to the scalp including (a) providing a composition in an applicator assembly, the applicator assembly including (i) a container for holding the composition; (ii) an extended tip actuator in fluid communication with the container, the extended tip actuator including (1) a base portion configured to fluidly connect the extended tip actuator to the container; and (2) a body portion configured to fluidly connect the base portion to a plurality of hollow tines; and (iii) an engine for delivering the composition from the container through the extended tip actuator; and (b) dispensing the composition from the applicator assembly directly onto the scalp. The tines each include a face located distally from the body portion. The tines each include an aperture in fluid communication with the container. The tines each have a protrusion length of from about 0.5 mm to about 100 mm. | 10-31-2013 |
20140191056 | METHOD FOR DELIVERING A VOLATILE MATERIAL - A method of delivering a volatile material to the atmosphere in a continuous manner is disclosed. The method includes providing a delivery engine having a reservoir that includes a volatile material mixture. The volatile material mixture includes about 40% to about 100%, by total weight, of the volatile materials each having a vapor pressure at 25° C. of less than about 0.1 ton. The delivery system also includes a microporous membrane enclosing the reservoir, wherein the microporous membrane comprises an average pore size of about 0.01 to about 0.03 microns. | 07-10-2014 |
20140197246 | APPARATUS FOR DELIVERING A VOLATILE MATERIAL - An apparatus for delivering a volatile material in a continuous manner is disclosed. The apparatus includes a delivery engine having a reservoir for containing a volatile material; a rupturable substrate secured to the reservoir; a rupture element positioned adjacent to the rupturable substrate; and a breathable membrane enclosing the reservoir, rupturable substrate and rupture element. In some embodiments, the apparatus includes a housing having a notch for compressing the rupture element and breaching the rupturable substrate as it is inserted into the housing. | 07-17-2014 |
20150059793 | Hair Treatment Method, Kit, Recipient, and Use Thereof - A method of treating hair, a hair treatment kit for extemporaneous preparation of hair treatment compositions, a recipient for applying hair treatment compositions, and use thereof are provided. The invention provides a superior hair treatment performance such as a superior hair colouring and/or bleaching performance, particularly for providing superior root to tip treatment evenness. | 03-05-2015 |
20150296953 | HAIR TREATMENT APPLICATION DELIVERY SYSTEM COMPRISING A COMPOSITION - A hair treatment application delivery system directed to at least one solid treatment composition comprising a wax and a silicone; and a hair treatment application delivery device comprising a first plate and a second plate positionable in a juxtaposed relationship when the hair treatment application delivery device is in a closed state, wherein the first and second plates are coupled together via a connection, and wherein the first and second plates each has an internal and external surface. | 10-22-2015 |
20160136316 | METHOD FOR DELIVERING A VOLATILE MATERIAL - A method of delivering a volatile material to the atmosphere in a continuous manner is disclosed. The method includes providing a delivery engine having a reservoir that includes a volatile material mixture. The volatile material mixture includes about 40% to about 100%, by total weight, of the volatile materials each having a vapor pressure at 25° C. of less than about 0.1 torr. The delivery system also includes a microporous membrane enclosing the reservoir, wherein the microporous membrane comprises an average pore size of about 0.01 to about 0.03 microns. | 05-19-2016 |
Patent application number | Description | Published |
20100114610 | Electronic Method and System That Improves Efficiencies for Rendering Diagnosis of Radiology Procedures - An electronic method and system for improving radiologists' efficiencies when viewing radiology procedures and rendering diagnosis in a manner that emulates current methods and apparatus. The method of the present invention includes reviewing electronic radiology images and reports contained in a patient's digital master folder (an information object invented to manage the patient's radiology information), comparing images from the current procedure to specific images from prior procedures in a specified order, and dictating the procedure's diagnosis into the digital master folder. The apparatus of the present invention includes a flat panel monitor for the viewing and manipulation of digital master folders, a dictation trackball device for manual and voice enabled operation and navigation of the system, and multiple high-resolution computer monitors functioning as a “light-box” for the viewing of radiology images. | 05-06-2010 |
20120265557 | Electronic Method and System that Improves Efficiencies for Rendering Diagnosis of Radiology Procedures - An electronic method and system for improving radiologists' efficiencies when viewing radiology procedures and rendering diagnosis in a manner that emulates current methods and apparatus. The method of the present invention includes reviewing electronic radiology images and reports contained in a patient's digital master folder (an information object invented to manage the patient's radiology information), comparing images from the current procedure to specific images from prior procedures in a specified order, and dictating the procedure's diagnosis into the digital master folder. The apparatus of the present invention includes a flat panel monitor for the viewing and manipulation of digital master folders, a dictation trackball device for manual and voice enabled operation and navigation of the system, and multiple high-resolution computer monitors functioning as a “light-box” for the viewing of radiology images. | 10-18-2012 |
20130317855 | Electronic Method and System that Improves Efficiencies for Rendering Diagnosis of Radiology Procedures - An electronic method and system for improving radiologists' efficiencies when viewing radiology procedures and rendering diagnosis in a manner that emulates current methods and apparatus. The method of the present invention includes reviewing electronic radiology images and reports contained in a patient's digital master folder (an information object invented to manage the patient's radiology information), comparing images from the current procedure to specific images from prior procedures in a specified order, and dictating the procedure's diagnosis into the digital master folder. The apparatus of the present invention includes a flat panel monitor for the viewing and manipulation of digital master folders, a dictation trackball device for manual and voice enabled operation and navigation of the system, and multiple high-resolution computer monitors functioning as a “light-box” for the viewing of radiology images. | 11-28-2013 |
20140195270 | Electronic Method and System that Improves Efficiencies for Rendering Diagnosis of Radiology Procedures - An electronic method and system for improving radiologists' efficiencies when viewing radiology procedures and rendering diagnosis in a manner that emulates current methods and apparatus. The method of the present invention includes reviewing electronic radiology images and reports contained in a patient's digital master folder (an information object invented to manage the patient's radiology information), comparing images from the current procedure to specific images from prior procedures in a specified order, and dictating the procedure's diagnosis into the digital master folder. The apparatus of the present invention includes a flat panel monitor for the viewing and manipulation of digital master folders, a dictation trackball device for manual and voice enabled operation and navigation of the system, and multiple high-resolution computer monitors functioning as a “light-box” for the viewing of radiology images. | 07-10-2014 |
20150234982 | Electronic Method and System that Improves Efficiencies for Rendering Diagnosis of Radiology Procedures - An electronic method and system for improving radiologists' efficiencies when viewing radiology procedures and rendering diagnosis in a manner that emulates current methods and apparatus. The method of the present invention includes reviewing electronic radiology images and reports contained in a patient's digital master folder (an information object invented to manage the patient's radiology information), comparing images from the current procedure to specific images from prior procedures in a specified order, and dictating the procedure's diagnosis into the digital master folder. The apparatus of the present invention includes a flat panel monitor for the viewing and manipulation of digital master folders, a dictation trackball device for manual and voice enabled operation and navigation of the system, and multiple high-resolution computer monitors functioning as a “light-box” for the viewing of radiology images. | 08-20-2015 |